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Wed, 22 May 2024 09:55:14 +0200 (CEST) Received: from augenblix2.phytec.de (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Wed, 22 May 2024 09:55:14 +0200 From: Wadim Egorov To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 4/5] board: phytec: common: Introduce a method to inject DDR timings deltas Date: Wed, 22 May 2024 09:55:04 +0200 Message-ID: <20240522075505.3339347-5-w.egorov@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240522075505.3339347-1-w.egorov@phytec.de> References: <20240522075505.3339347-1-w.egorov@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Berlix.phytec.de (172.25.0.12) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKIsWRmVeSWpSXmKPExsWyRpKBR/fREt80g1cNEhbvT01kt5j75gCr xYH+XkaLlrUeFg+v+ls862xitrh8/yarxaUHqRanGltZLF4cm8tu0f//OZPFmx9nmSy+bdnG aDF10mZ2i7d7O9ktut+pOwh4rP14n9Xj/Y1Wdo/ZDRdZPHbOusvu8erAKnaPs3d2MHr0d7ew evy5+I7V4/iN7Uwem155BHBFcdmkpOZklqUW6dslcGU0XljCWrBFreL2ujVMDYyv5LsYOTkk BEwkrn06xdzFyMUhJLCESWLSj38sEM5jRomZrzaxgVSxCahL3NnwjRXEFhEwk1i09jwbSBGz wBEmicen9jGCJIQF4iQmnboLZHNwsAioSmyabAwS5hWwlLhwfQoTxDZ5iZmXvrOD2JwCVhIz tqxhAbGFgGpOX57ADFEvKHFy5hOwODNQffPW2cwQtoTEwRcvmCHq5SVeXFrOAjNz2rnXzBB2 qMTWL9uZJjAKzUIyahaSUbOQjFrAyLyKUSg3Mzk7tSgzW68go7IkNVkvJXUTIygqRRi4djD2 zfE4xMjEwXiIUYKDWUmEd9MWzzQh3pTEyqrUovz4otKc1OJDjNIcLErivKs7glOFBNITS1Kz U1MLUotgskwcnFINjGvjDy35/ehQcfv2NQELA24tksxNM+23ea+yV1au6ucH/b9Tb8yuYxXR W6zC8DzyaOOkNWvNHwV2HXi4g2XpnBdxWgsnvntwluHXwob0M5mL/E78ndz968eut8GGMnsj tks90WJfyr1X+s7Eum/ubUfDw1jYwwzOL2Tm8PB7omZh6G+eGLZWKFmJpTgj0VCLuag4EQCE FY7VuAIAAA== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Introduce fdt_apply_ddrss_timings_patch() to allow board code to override DDR settings in the device tree prior to DDRSS driver probing. Signed-off-by: Wadim Egorov Tested-by: John Ma --- v2: - Make board/phytec/common/k3 always compile for CONFIG_ARCH_K3 --- board/phytec/common/Makefile | 4 +- board/phytec/common/k3/Makefile | 1 + board/phytec/common/k3/k3_ddrss_patch.c | 68 +++++++++++++++++++++++++ board/phytec/common/k3/k3_ddrss_patch.h | 28 ++++++++++ board/phytec/phycore_am62x/MAINTAINERS | 1 + 5 files changed, 99 insertions(+), 3 deletions(-) create mode 100644 board/phytec/common/k3/k3_ddrss_patch.c create mode 100644 board/phytec/common/k3/k3_ddrss_patch.h diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index c34fc503059..988c5742db5 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -5,10 +5,8 @@ ifdef CONFIG_SPL_BUILD # necessary to create built-in.o obj- := __dummy__.o -else -obj-$(CONFIG_ARCH_K3) += k3/ endif obj-y += phytec_som_detection.o -obj-$(CONFIG_ARCH_K3) += am6_som_detection.o +obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/ obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile index bcca1a9f846..40e91a43e99 100644 --- a/board/phytec/common/k3/Makefile +++ b/board/phytec/common/k3/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += board.o +obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o diff --git a/board/phytec/common/k3/k3_ddrss_patch.c b/board/phytec/common/k3/k3_ddrss_patch.c new file mode 100644 index 00000000000..39f7be8dc92 --- /dev/null +++ b/board/phytec/common/k3/k3_ddrss_patch.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + */ + +#include "k3_ddrss_patch.h" + +#include +#include + +#ifdef CONFIG_K3_AM64_DDRSS +#define LPDDR4_INTR_CTL_REG_COUNT (423U) +#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U) +#endif + +static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset, + const char *name, uint32_t idx, u32 val) +{ + val = cpu_to_be32(val); + return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name, + strlen(name), + idx * sizeof(val), &val, + sizeof(val)); +} + +int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss) +{ + int i, j; + int ret; + int mem_offset; + + mem_offset = fdt_path_offset(fdt, "/memorycontroller@f300000"); + if (mem_offset < 0) + return -ENODEV; + + for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++) + for (j = 0; j < ddrss->ctl_regs_num; j++) + if (i == ddrss->ctl_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,ctl-data", i, + ddrss->ctl_regs[j].val); + if (ret) + return ret; + } + + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) + for (j = 0; j < ddrss->pi_regs_num; j++) + if (i == ddrss->pi_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,pi-data", i, + ddrss->pi_regs[j].val); + if (ret) + return ret; + } + + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) + for (j = 0; j < ddrss->phy_regs_num; j++) + if (i == ddrss->phy_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,phy-data", i, + ddrss->phy_regs[j].val); + if (ret) + return ret; + } + + return 0; +} diff --git a/board/phytec/common/k3/k3_ddrss_patch.h b/board/phytec/common/k3/k3_ddrss_patch.h new file mode 100644 index 00000000000..0a47c85116a --- /dev/null +++ b/board/phytec/common/k3/k3_ddrss_patch.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + */ + +#ifndef K3_DDRSS_PATCH +#define K3_DDRSS_PATCH + +#include + +struct ddr_reg { + u32 off; + u32 val; +}; + +struct ddrss { + struct ddr_reg *ctl_regs; + u32 ctl_regs_num; + struct ddr_reg *pi_regs; + u32 pi_regs_num; + struct ddr_reg *phy_regs; + u32 phy_regs_num; +}; + +int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss); + +#endif /* K3_DDRSS_PATCH */ diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS index 02ac88e58a4..42463ad054e 100644 --- a/board/phytec/phycore_am62x/MAINTAINERS +++ b/board/phytec/phycore_am62x/MAINTAINERS @@ -11,3 +11,4 @@ F: configs/phycore_am62x_a53_defconfig F: configs/phycore_am62x_r5_defconfig F: include/configs/phycore_am62x.h F: doc/board/phytec/phycore-am62x.rst +F: board/phytec/common/k3