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Mon, 13 May 2024 14:13:14 -0400 (EDT) From: Jiaxun Yang Date: Mon, 13 May 2024 19:13:02 +0100 Subject: [PATCH 05/13] ahci: dwc_ahsata: Generalize the driver MIME-Version: 1.0 Message-Id: <20240513-boston-v1-5-fac96938417e@flygoat.com> References: <20240513-boston-v1-0-fac96938417e@flygoat.com> In-Reply-To: <20240513-boston-v1-0-fac96938417e@flygoat.com> To: u-boot@lists.denx.de Cc: Michal Simek , Tom Rini , Daniel Schwierzeck , Paul Burton , Simon Glass , Lukasz Majewski , Sean Anderson , Sumit Garg , Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3395; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=kc074xhaq5eZqjHZFuP2QtfsC7eLQ/HYuVNInznPrIM=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjSnCONVTJND3k5y8d+7zf7P9mfTlHd6Js1fWjZ1U99SI 51Vea0nOkpZGMQ4GGTFFFlCBJT6NjReXHD9QdYfmDmsTCBDGLg4BeAmdzD8z9w/o/aJJ6+9h6ku j7bWLe3qP5unWr27fXTenrzDOpHHrBgZWlJjr73ZuJl1v2aplXX8EomzD156RYhNXZ1gp1X04nE yAwA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 X-Mailman-Approved-At: Mon, 13 May 2024 20:17:26 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Remove hard dependencies to arch headers, get clock from clk subsystem if arch clock function is not available, align compatible strings with devicetree binding. No functional change on existing platforms, just get it build on other platforms. Signed-off-by: Jiaxun Yang --- drivers/ata/dwc_ahsata.c | 38 ++++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index c2cde48c0b55..cef95e76c642 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -18,9 +19,11 @@ #include #include #include +#if IS_ENABLED(CONFIG_ARCH_MX5) || IS_ENABLED(CONFIG_ARCH_MX6) #include #include #include +#endif #include #include #include @@ -115,13 +118,12 @@ static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk) return 0; } -static int ahci_host_init(struct ahci_uc_priv *uc_priv) +static int ahci_host_init(struct ahci_uc_priv *uc_priv, int clk) { u32 tmp, cap_save, num_ports; int i, j, timeout = 1000; struct sata_port_regs *port_mmio = NULL; struct sata_host_regs *host_mmio = uc_priv->mmio_base; - int clk = mxc_get_clock(MXC_SATA_CLK); cap_save = readl(&host_mmio->cap); cap_save |= SATA_HOST_CAP_SSS; @@ -909,17 +911,41 @@ int dwc_ahsata_scan(struct udevice *dev) int dwc_ahsata_probe(struct udevice *dev) { struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk_bulk clk_bulk; + struct clk clk; + int sataclk; int ret; -#if defined(CONFIG_MX6) +#if IS_ENABLED(CONFIG_MX6) setup_sata(); #endif +#if IS_ENABLED(CONFIG_MX5) || IS_ENABLED(CONFIG_MX6) + sataclk = mxc_get_clock(MXC_SATA_CLK); +#else + ret = clk_get_bulk(dev, &clk_bulk); + if (ret) + return ret; + + ret = clk_enable_bulk(&clk_bulk); + if (ret) + return ret; + + ret = clk_get_by_name(dev, "sata", &clk); + if (ret) + return ret; + + sataclk = clk_get_rate(&clk); +#endif + if (IS_ERR_VALUE(sataclk)) { + log_err("Unable to get SATA clock rate\n"); + return -EINVAL; + } uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI; uc_priv->mmio_base = dev_read_addr_ptr(dev); /* initialize adapter */ - ret = ahci_host_init(uc_priv); + ret = ahci_host_init(uc_priv, sataclk); if (ret) return ret; @@ -961,7 +987,6 @@ U_BOOT_DRIVER(dwc_ahsata_blk) = { .ops = &dwc_ahsata_blk_ops, }; -#if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI) struct ahci_ops dwc_ahsata_ahci_ops = { .port_status = dwc_ahsata_port_status, .reset = dwc_ahsata_bus_reset, @@ -969,7 +994,9 @@ struct ahci_ops dwc_ahsata_ahci_ops = { }; static const struct udevice_id dwc_ahsata_ahci_ids[] = { + { .compatible = "fsl,imx53-ahci" }, { .compatible = "fsl,imx6q-ahci" }, + { .compatible = "fsl,imx6qp-ahci" }, { } }; @@ -980,4 +1007,3 @@ U_BOOT_DRIVER(dwc_ahsata_ahci) = { .ops = &dwc_ahsata_ahci_ops, .probe = dwc_ahsata_probe, }; -#endif