diff mbox series

[08/11] spi: cadence-quadspi: Direct mode does not support zero length addresses

Message ID 20240411223709.573-9-greg.malysa@timesys.com
State Deferred
Delegated to: Tom Rini
Headers show
Series cadence-qspi: Add DTR support including PHY mode calibration | expand

Commit Message

Greg Malysa April 11, 2024, 10:36 p.m. UTC 
From: Ian Roberts <ian.roberts@timesys.com>

It is not possible to configure the Cadence SPI IP block to use a zero
length address in DMA read or write commands.

Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Greg Malysa <greg.malysa@timesys.com>
Signed-off-by: Ian Roberts <ian.roberts@timesys.com>
---

 drivers/spi/cadence_qspi_apb.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 2600370f85..340889c271 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -784,7 +784,7 @@  int cadence_qspi_apb_read_execute(struct cadence_spi_priv *priv,
 
 	cadence_qspi_apb_enable_linear_mode(true);
 
-	if (priv->use_dac_mode && (from + len < priv->ahbsize)) {
+	if (op->addr.nbytes && priv->use_dac_mode && (from + len < priv->ahbsize)) {
 		if (len < 256 ||
 		    dma_memcpy(buf, priv->ahbbase + from, len) < 0) {
 			memcpy_fromio(buf, priv->ahbbase + from, len);
@@ -970,7 +970,7 @@  int cadence_qspi_apb_write_execute(struct cadence_spi_priv *priv,
 	size_t len = op->data.nbytes;
 
 	cadence_qspi_apb_enable_linear_mode(true);
-	if (priv->use_dac_mode && (to + len < priv->ahbsize)) {
+	if (op->addr.nbytes && priv->use_dac_mode && (to + len < priv->ahbsize)) {
 		memcpy_toio(priv->ahbbase + to, buf, len);
 		if (!cadence_qspi_wait_idle(priv->regbase))
 			return -EIO;