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Thu, 11 Apr 2024 15:37:44 -0700 (PDT) Received: from executor.attlocal.net ([2600:1700:5eb5:1ba0:dc1f:cff:fef9:435b]) by smtp.gmail.com with ESMTPSA id q11-20020a25f90b000000b00dcbbea79ffcsm482744ybe.42.2024.04.11.15.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 15:37:43 -0700 (PDT) From: Greg Malysa To: u-boot@lists.denx.de Cc: Arturs.Artamonovs@analog.com, Vasileios.Bimpikas@analog.com, Utsav.Agarwal@analog.com, Ian Roberts , Nathan Barrett-Morrison , Greg Malysa , Apurva Nandan , Ashok Reddy Soma , Dhruva Gole , Igor Prusov , Jagan Teki , Jan Kiszka , Johan Jonker , Tejas Bhumkar , Tom Rini , Udit Kumar Subject: [PATCH 07/11] spi: cadence-quadspi: Remove redundant DTR state Date: Thu, 11 Apr 2024 18:36:51 -0400 Message-ID: <20240411223709.573-8-greg.malysa@timesys.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240411223709.573-1-greg.malysa@timesys.com> References: <20240411223709.573-1-greg.malysa@timesys.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Ian Roberts cadence_spi_mem_supports_op() already checks that every memory operation either has all DTR booleans set or cleared. Thus, there is no need to store a cached dtr value. The command DTR state can be used since it is not optional like the other fields. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers/spi/cadence_qspi.c | 6 ++++++ drivers/spi/cadence_qspi.h | 1 - drivers/spi/cadence_qspi_apb.c | 27 ++++++++------------------- 3 files changed, 14 insertions(+), 20 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index f4593c47b8..a2644d9e11 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -362,6 +362,12 @@ static bool cadence_spi_mem_supports_op(struct spi_slave *slave, bool all_true, all_false; /* + * For an op to be DTR, cmd phase along with every other non-empty + * phase should have dtr field set to 1. If an op phase has zero + * nbytes, ignore its dtr field; otherwise, check its dtr field. + * Also, dummy checks not performed here Since supports_op() + * already checks that all or none of the fields are DTR. + * * op->dummy.dtr is required for converting nbytes into ncycles. * Also, don't check the dtr field of the op phase having zero nbytes. */ diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 355919cb23..5704f5a3f6 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -265,7 +265,6 @@ struct cadence_spi_priv { u8 inst_width; u8 addr_width; u8 data_width; - bool dtr; }; /* Functions call declaration */ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index d347cb8d47..2600370f85 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -120,17 +120,6 @@ static int cadence_qspi_set_protocol(struct cadence_spi_priv *priv, { int ret; - /* - * For an op to be DTR, cmd phase along with every other non-empty - * phase should have dtr field set to 1. If an op phase has zero - * nbytes, ignore its dtr field; otherwise, check its dtr field. - * Also, dummy checks not performed here Since supports_op() - * already checks that all or none of the fields are DTR. - */ - priv->dtr = op->cmd.dtr && - (!op->addr.nbytes || op->addr.dtr) && - (!op->data.nbytes || op->data.dtr); - ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth); if (ret < 0) return ret; @@ -449,7 +438,7 @@ int cadence_qspi_apb_command_read_setup(struct cadence_spi_priv *priv, return ret; ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_STIG_LSB, - priv->dtr); + op->cmd.dtr); if (ret) return ret; @@ -484,13 +473,13 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv, return log_msg_ret("QSPI: Invalid command length", -EINVAL); } - if (opcode == CMD_4BYTE_OCTAL_READ && !priv->dtr) + if (opcode == CMD_4BYTE_OCTAL_READ && !op->cmd.dtr) opcode = CMD_4BYTE_FAST_READ; reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; /* Set up dummy cycles. */ - dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr); + dummy_clk = cadence_qspi_calc_dummy(op, op->cmd.dtr); if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) return -ENOTSUPP; @@ -547,7 +536,7 @@ int cadence_qspi_apb_command_write_setup(struct cadence_spi_priv *priv, return ret; ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_STIG_LSB, - priv->dtr); + op->cmd.dtr); if (ret) return ret; @@ -597,7 +586,7 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, } /* Set up dummy cycles. */ - dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr); + dummy_clk = cadence_qspi_calc_dummy(op, op->cmd.dtr); if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) return -EOPNOTSUPP; @@ -645,7 +634,7 @@ int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv, return ret; ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_READ_LSB, - priv->dtr); + op->cmd.dtr); if (ret) return ret; @@ -673,7 +662,7 @@ int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv, if (dummy_bytes) { /* Convert to clock cycles. */ - dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr); + dummy_clk = cadence_qspi_calc_dummy(op, op->cmd.dtr); if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) return -ENOTSUPP; @@ -821,7 +810,7 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv, return ret; ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_WRITE_LSB, - priv->dtr); + op->cmd.dtr); if (ret) return ret;