diff mbox series

[07/11] spi: cadence-quadspi: Remove redundant DTR state

Message ID 20240411223709.573-8-greg.malysa@timesys.com
State Deferred
Delegated to: Tom Rini
Headers show
Series cadence-qspi: Add DTR support including PHY mode calibration | expand

Commit Message

Greg Malysa April 11, 2024, 10:36 p.m. UTC 
From: Ian Roberts <ian.roberts@timesys.com>

cadence_spi_mem_supports_op() already checks that every memory operation
either has all DTR booleans set or cleared. Thus, there is no need to
store a cached dtr value. The command DTR state can be used since it is
not optional like the other fields.

Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Greg Malysa <greg.malysa@timesys.com>
Signed-off-by: Ian Roberts <ian.roberts@timesys.com>
---

 drivers/spi/cadence_qspi.c     |  6 ++++++
 drivers/spi/cadence_qspi.h     |  1 -
 drivers/spi/cadence_qspi_apb.c | 27 ++++++++-------------------
 3 files changed, 14 insertions(+), 20 deletions(-)
diff mbox series

Patch

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index f4593c47b8..a2644d9e11 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -362,6 +362,12 @@  static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
 	bool all_true, all_false;
 
 	/*
+	 * For an op to be DTR, cmd phase along with every other non-empty
+	 * phase should have dtr field set to 1. If an op phase has zero
+	 * nbytes, ignore its dtr field; otherwise, check its dtr field.
+	 * Also, dummy checks not performed here Since supports_op()
+	 * already checks that all or none of the fields are DTR.
+	 *
 	 * op->dummy.dtr is required for converting nbytes into ncycles.
 	 * Also, don't check the dtr field of the op phase having zero nbytes.
 	 */
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 355919cb23..5704f5a3f6 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -265,7 +265,6 @@  struct cadence_spi_priv {
 	u8		inst_width;
 	u8		addr_width;
 	u8		data_width;
-	bool		dtr;
 };
 
 /* Functions call declaration */
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index d347cb8d47..2600370f85 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -120,17 +120,6 @@  static int cadence_qspi_set_protocol(struct cadence_spi_priv *priv,
 {
 	int ret;
 
-	/*
-	 * For an op to be DTR, cmd phase along with every other non-empty
-	 * phase should have dtr field set to 1. If an op phase has zero
-	 * nbytes, ignore its dtr field; otherwise, check its dtr field.
-	 * Also, dummy checks not performed here Since supports_op()
-	 * already checks that all or none of the fields are DTR.
-	 */
-	priv->dtr = op->cmd.dtr &&
-		    (!op->addr.nbytes || op->addr.dtr) &&
-		    (!op->data.nbytes || op->data.dtr);
-
 	ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth);
 	if (ret < 0)
 		return ret;
@@ -449,7 +438,7 @@  int cadence_qspi_apb_command_read_setup(struct cadence_spi_priv *priv,
 		return ret;
 
 	ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_STIG_LSB,
-				      priv->dtr);
+				      op->cmd.dtr);
 	if (ret)
 		return ret;
 
@@ -484,13 +473,13 @@  int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv,
 		return log_msg_ret("QSPI: Invalid command length", -EINVAL);
 	}
 
-	if (opcode == CMD_4BYTE_OCTAL_READ && !priv->dtr)
+	if (opcode == CMD_4BYTE_OCTAL_READ && !op->cmd.dtr)
 		opcode = CMD_4BYTE_FAST_READ;
 
 	reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 
 	/* Set up dummy cycles. */
-	dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr);
+	dummy_clk = cadence_qspi_calc_dummy(op, op->cmd.dtr);
 	if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 		return -ENOTSUPP;
 
@@ -547,7 +536,7 @@  int cadence_qspi_apb_command_write_setup(struct cadence_spi_priv *priv,
 		return ret;
 
 	ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_STIG_LSB,
-				      priv->dtr);
+				      op->cmd.dtr);
 	if (ret)
 		return ret;
 
@@ -597,7 +586,7 @@  int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv,
 	}
 
 	/* Set up dummy cycles. */
-	dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr);
+	dummy_clk = cadence_qspi_calc_dummy(op, op->cmd.dtr);
 	if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 		return -EOPNOTSUPP;
 
@@ -645,7 +634,7 @@  int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv,
 		return ret;
 
 	ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_READ_LSB,
-				      priv->dtr);
+				      op->cmd.dtr);
 	if (ret)
 		return ret;
 
@@ -673,7 +662,7 @@  int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv,
 
 	if (dummy_bytes) {
 		/* Convert to clock cycles. */
-		dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr);
+		dummy_clk = cadence_qspi_calc_dummy(op, op->cmd.dtr);
 
 		if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 			return -ENOTSUPP;
@@ -821,7 +810,7 @@  int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv,
 		return ret;
 
 	ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_WRITE_LSB,
-				      priv->dtr);
+				      op->cmd.dtr);
 	if (ret)
 		return ret;