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Thu, 11 Apr 2024 15:37:42 -0700 (PDT) Received: from executor.attlocal.net ([2600:1700:5eb5:1ba0:dc1f:cff:fef9:435b]) by smtp.gmail.com with ESMTPSA id q11-20020a25f90b000000b00dcbbea79ffcsm482744ybe.42.2024.04.11.15.37.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 15:37:42 -0700 (PDT) From: Greg Malysa To: u-boot@lists.denx.de Cc: Arturs.Artamonovs@analog.com, Vasileios.Bimpikas@analog.com, Utsav.Agarwal@analog.com, Ian Roberts , Nathan Barrett-Morrison , Greg Malysa , Apurva Nandan , Dhruva Gole , Jagan Teki , Jan Kiszka , Tejas Bhumkar , Tom Rini , Udit Kumar Subject: [PATCH 05/11] spi: cadence-quadspi: disable automatic write enable Date: Thu, 11 Apr 2024 18:36:49 -0400 Message-ID: <20240411223709.573-6-greg.malysa@timesys.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240411223709.573-1-greg.malysa@timesys.com> References: <20240411223709.573-1-greg.malysa@timesys.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Ian Roberts The spi-nor subsystem issues the write enable command manually. So this automatic feature sends duplicate commands and also introduces the possibility of erroneous writes. Disable the automatic write enable feature by default. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 72e92cc997..355919cb23 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -73,6 +73,7 @@ #define CQSPI_REG_WR_INSTR 0x08 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_WR_INSTR_WELDIS_MASK BIT(8) #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index eb9f4ed63d..176cff5338 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -842,6 +842,7 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv, } reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; + reg |= CQSPI_REG_WR_INSTR_WELDIS_MASK; reg |= priv->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; reg |= priv->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; writel(reg, priv->regbase + CQSPI_REG_WR_INSTR);