diff mbox series

[05/11] spi: cadence-quadspi: disable automatic write enable

Message ID 20240411223709.573-6-greg.malysa@timesys.com
State Deferred
Delegated to: Tom Rini
Headers show
Series cadence-qspi: Add DTR support including PHY mode calibration | expand

Commit Message

Greg Malysa April 11, 2024, 10:36 p.m. UTC 
From: Ian Roberts <ian.roberts@timesys.com>

The spi-nor subsystem issues the write enable command manually. So
this automatic feature sends duplicate commands and also introduces
the possibility of erroneous writes.

Disable the automatic write enable feature by default.

Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Greg Malysa <greg.malysa@timesys.com>
Signed-off-by: Ian Roberts <ian.roberts@timesys.com>
---

 drivers/spi/cadence_qspi.h     | 1 +
 drivers/spi/cadence_qspi_apb.c | 1 +
 2 files changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 72e92cc997..355919cb23 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -73,6 +73,7 @@ 
 
 #define CQSPI_REG_WR_INSTR                      0x08
 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
+#define CQSPI_REG_WR_INSTR_WELDIS_MASK		BIT(8)
 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB	12
 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB	16
 
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index eb9f4ed63d..176cff5338 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -842,6 +842,7 @@  int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv,
 	}
 
 	reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
+	reg |= CQSPI_REG_WR_INSTR_WELDIS_MASK;
 	reg |= priv->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
 	reg |= priv->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
 	writel(reg, priv->regbase + CQSPI_REG_WR_INSTR);