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Thu, 11 Apr 2024 15:37:41 -0700 (PDT) Received: from executor.attlocal.net ([2600:1700:5eb5:1ba0:dc1f:cff:fef9:435b]) by smtp.gmail.com with ESMTPSA id q11-20020a25f90b000000b00dcbbea79ffcsm482744ybe.42.2024.04.11.15.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 15:37:41 -0700 (PDT) From: Greg Malysa To: u-boot@lists.denx.de Cc: Arturs.Artamonovs@analog.com, Vasileios.Bimpikas@analog.com, Utsav.Agarwal@analog.com, Ian Roberts , Nathan Barrett-Morrison , Greg Malysa , Apurva Nandan , Dhruva Gole , Jagan Teki , Jan Kiszka , Neha Malcom Francis , Tejas Bhumkar , Tom Rini , Udit Kumar Subject: [PATCH 03/11] spi: cadence-quadspi: Enable DDR bit for DTR commands Date: Thu, 11 Apr 2024 18:36:47 -0400 Message-ID: <20240411223709.573-4-greg.malysa@timesys.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240411223709.573-1-greg.malysa@timesys.com> References: <20240411223709.573-1-greg.malysa@timesys.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Ian Roberts The Cadence octal SPI IP read instruction register requires a bit to be set to indicate if the read opcode is a compliant DDR read command. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 693474a287..72e92cc997 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -61,6 +61,7 @@ #define CQSPI_REG_RD_INSTR 0x04 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 +#define CQSPI_REG_RD_INSTR_DDR_EN_MASK BIT(10) #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index fb90532217..34cacf1880 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -446,6 +446,7 @@ int cadence_qspi_apb_command_read_setup(struct cadence_spi_priv *priv, return ret; reg = cadence_qspi_calc_rdreg(priv); + reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0; writel(reg, priv->regbase + CQSPI_REG_RD_INSTR); return 0; @@ -537,6 +538,7 @@ int cadence_qspi_apb_command_write_setup(struct cadence_spi_priv *priv, return ret; reg = cadence_qspi_calc_rdreg(priv); + reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0; writel(reg, priv->regbase + CQSPI_REG_RD_INSTR); return 0; @@ -638,6 +640,7 @@ int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv, opcode = op->cmd.opcode; rd_reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; + rd_reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0; rd_reg |= cadence_qspi_calc_rdreg(priv); writel(op->addr.val, priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); @@ -812,6 +815,7 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv, writel(reg, priv->regbase + CQSPI_REG_WR_INSTR); reg = cadence_qspi_calc_rdreg(priv); + reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0; writel(reg, priv->regbase + CQSPI_REG_RD_INSTR); writel(op->addr.val, priv->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);