| Message ID | 20240128063746.1552081-1-tejas.arvind.bhumkar@amd.com |
|---|---|
| State | Accepted |
| Commit | b4b0228db8408af56472ceeae279693073ed2204 |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | [v2] spi: cadence_qspi: Address the comparison failure for 0-8 bytes of data | expand |
On Sun, Jan 28, 2024 at 12:08 PM Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> wrote: > > The current implementation encounters issues when testing data ranging > from 0 to 8 bytes. This was confirmed through testing with both ISSI > (IS25WX256) and Micron (MT35XU02G) Flash exclusively in SDR mode. > > Upon investigation, it was observed that utilizing the > "SPI_NOR_OCTAL_READ" flag and attempting to read less than 8 bytes in > STIG mode results in a read failure, leading to a compare test failure. > > To resolve this issue, the CMD_4BYTE_FAST_READ opcode is now utilized > instead of CMD_4BYTE_OCTAL_READ, specifically in SDR mode. > > This is based on patch series: > https://lore.kernel.org/all/cover.1701853668.git.tejas.arvind.bhumkar@amd.com/ > > Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> > --- Applied to u-boot-spi/master
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index e02a3b3de3..c2be307f1d 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -18,9 +18,6 @@ #include "cadence_qspi.h" #include <dt-bindings/power/xlnx-versal-power.h> -#define CMD_4BYTE_READ 0x13 -#define CMD_4BYTE_FAST_READ 0x0C - int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, const struct spi_mem_op *op) { diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 12825f8911..693474a287 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -33,6 +33,10 @@ #define CQSPI_DUMMY_BYTES_MAX 4 #define CQSPI_DUMMY_CLKS_MAX 31 +#define CMD_4BYTE_FAST_READ 0x0C +#define CMD_4BYTE_OCTAL_READ 0x7c +#define CMD_4BYTE_READ 0x13 + /**************************************************************************** * Controller's configuration and status register (offset from QSPI_BASE) ****************************************************************************/ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index d033184aa4..fb90532217 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -469,6 +469,9 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv, else opcode = op->cmd.opcode; + if (opcode == CMD_4BYTE_OCTAL_READ && !priv->dtr) + opcode = CMD_4BYTE_FAST_READ; + reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; /* Set up dummy cycles. */
The current implementation encounters issues when testing data ranging from 0 to 8 bytes. This was confirmed through testing with both ISSI (IS25WX256) and Micron (MT35XU02G) Flash exclusively in SDR mode. Upon investigation, it was observed that utilizing the "SPI_NOR_OCTAL_READ" flag and attempting to read less than 8 bytes in STIG mode results in a read failure, leading to a compare test failure. To resolve this issue, the CMD_4BYTE_FAST_READ opcode is now utilized instead of CMD_4BYTE_OCTAL_READ, specifically in SDR mode. This is based on patch series: https://lore.kernel.org/all/cover.1701853668.git.tejas.arvind.bhumkar@amd.com/ Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> --- Changes in v2: - Resolve the duplication in the usage of the macro definition. drivers/spi/cadence_ospi_versal.c | 3 --- drivers/spi/cadence_qspi.h | 4 ++++ drivers/spi/cadence_qspi_apb.c | 3 +++ 3 files changed, 7 insertions(+), 3 deletions(-)