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Tue, 5 Dec 2023 21:34:02 -0800 Received: from xhdcl190040.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34 via Frontend Transport; Tue, 5 Dec 2023 23:34:00 -0600 From: Tejas Bhumkar To: CC: , , , , , , "T Karthik Reddy" Subject: [PATCH 10/30] mtd: spi-nor: program quad enable bit for winbond flashes Date: Wed, 6 Dec 2023 11:03:44 +0530 Message-ID: <20231206053353.3745918-1-tejas.arvind.bhumkar@amd.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD4:EE_|SJ2PR12MB9113:EE_ X-MS-Office365-Filtering-Correlation-Id: 59256add-5fde-4aa9-92e3-08dbf61cf50f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: O7+z5rqpvoRgKOlQ96hohxTx4rC8jb7yihLgy4O/v4rgiwBEs1DqohmSDvb4AI6Qt29fJ/5TVKplxb8Ea+ttkjxb8pD9Nwu+8+/ZBMuWG1kZ1UXSdBn+z+bUxZ5bO/R7Ii0B5IrjX7xAPDB+/H0dMS1Lho7NBCK70TbLocwujeWgB9kGsudmvX3PKbrPFUkIYx4ZyDe3PwtSNSYTBWtpltgdN+DwcQuJxK3I8/Xi2yKFBEz5Fzce5H/r+pEGwLXC3xmQAfhjQlcviZZrD8z2WQsIk9H1XIhfoeHcgE4r6lNzZnrfJrhmuQBM8sF/h5gb1/3yZlFVabTl9rd7KWVM4n3Qg7F9gh9JJmJ6ir98J51UPmughv4AipZY7chktO/g636uuJtky//CF5gMbiO1l15wwexPTCRHv0TY5RADXdJAU9Xhjd5L5Hdel6p3U2SHIugMh39bRVQLDJtmsaM8Uidy1J1ixTJpZczNwUokEps28kKocRWioYu1x3W63d2JJoDHhjzLhUho+MLUixUoV7IJM/RQst5EtSNZJG2toFlFjc04Sy4RKsMCXHU8sSvDSI9qVEfDhS8ry0xbHR3iqwZENSPnpge9/+v1IevqxOpEMKKpmQtFw4r8fODCZgFJTmM55AF66n4G0LZFEGlUGcSzfdrWe+4kVY5n32X/gMU+RfX9iI7q3TGwmzzJVVIDn4jPdrj6/woLP8irkheXM/5csOWIZX5b2ZAIxeci/MfgGQ8IFTQxdd+D9yZErN7JmvanjqkfqLTdgaWaKuUdKw== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Previously, the quad enable function from Spansion was used for this purpose. However, for Winbond flash memory, the quad enable bit is configured by programming the Write Status Register-2 (SR-2) rather than the Configuration Register (CR). Signed-off-by: T Karthik Reddy Co-developed-by: Tejas Bhumkar Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 48 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 50 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index ace5da9591..454ae6cd4e 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2141,6 +2141,49 @@ static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) return 0; } +/** + * winbond_quad_enable() - Set QE bit in status register-2 + * @nor: pointer to a 'struct spi_nor' + * + * Return: 0 on success, -errno otherwise. + */ +static int winbond_quad_enable(struct spi_nor *nor) +{ + int ret; + u8 cr = 0; + + /* Check current Quad Enable bit value. */ + cr = read_cr(nor); + if (cr < 0) { + dev_dbg(nor->dev, + "error while reading configuration register\n"); + return -EINVAL; + } + + if (cr & SR2_QUAD_EN_BIT1) + return 0; + + cr |= SR2_QUAD_EN_BIT1; + + write_enable(nor); + + ret = nor->write_reg(nor, SPINOR_OP_WIN_WRSR2, &cr, 1); + if (ret < 0) { + dev_dbg(nor->dev, + "error while writing configuration register\n"); + return -EINVAL; + } + + ret = spi_nor_wait_till_ready(nor); + if (ret) { + dev_dbg(nor->dev, + "timeout while writing configuration register\n"); + return ret; + } + + return write_disable(nor); +} + /** * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. * @nor: pointer to a 'struct spi_nor' @@ -3052,6 +3095,11 @@ static int spi_nor_init_params(struct spi_nor *nor, case SNOR_MFR_MICRON: break; +#if defined(CONFIG_SPI_FLASH_WINBOND) + case SNOR_MFR_WINBOND: + params->quad_enable = winbond_quad_enable; + break; +#endif default: #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) /* Kept only for backward compatibility purpose. */ diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 72206f51ad..34e0aedc24 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -48,6 +48,7 @@ #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */ #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */ +#define SPINOR_OP_WIN_WRSR2 0x31 /* Winbond Write status register 2 */ #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */ @@ -187,6 +188,7 @@ /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT7 BIT(7) +#define SR2_QUAD_EN_BIT1 BIT(1) /* Winbond Quad I/O */ /* * Maximum number of flashes that can be connected