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Ip=[20.160.56.81]; Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR05FT019.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR03MB6568 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean U-Boot runs in supervisor mode. On ARMv6 and lower, software interrupts are taken in supervisor mode. When entering an interrupt, the link register is set to the address of the next instruction. However, if we are already in supervisor mode, this clobbers the link register. The debugger can't help us, since by the time it notices we've taken a software interrupt, the link register is already gone. Work around this by moving the return addres to another register. Signed-off-by: Sean Anderson --- arch/arm/lib/semihosting.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/lib/semihosting.S b/arch/arm/lib/semihosting.S index 393aade94a5..6e1691a832c 100644 --- a/arch/arm/lib/semihosting.S +++ b/arch/arm/lib/semihosting.S @@ -18,11 +18,17 @@ ENTRY(smh_trap) #elif defined(CONFIG_SYS_THUMB_BUILD) svc #0xab #else +#if CONFIG_SYS_ARM_ARCH < 7 + /* Before the ARMv7 exception model, svc (swi) clobbers lr */ + mov r2, lr +#endif svc #0x123456 #endif #if defined(CONFIG_ARM64) ret +#elif CONFIG_SYS_ARM_ARCH < 7 + bx r2 #else bx lr #endif