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[2/3] arm: semihosting: Fix returning from traps on ARMv6 and lower

Message ID 20231027204015.1547595-3-sean.anderson@seco.com
State Accepted
Commit 6ef83ab6be8978ab85a7d8967e9585ddf5f2bbbd
Delegated to: Tom Rini
Headers show
Series arm: Semihosting fixes/improvements for ARMv6 and older | expand

Commit Message

Sean Anderson Oct. 27, 2023, 8:40 p.m. UTC 
U-Boot runs in supervisor mode. On ARMv6 and lower, software interrupts
are taken in supervisor mode. When entering an interrupt, the link
register is set to the address of the next instruction. However, if we
are already in supervisor mode, this clobbers the link register. The
debugger can't help us, since by the time it notices we've taken a
software interrupt, the link register is already gone. Work around this
by moving the return addres to another register.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

 arch/arm/lib/semihosting.S | 6 ++++++
 1 file changed, 6 insertions(+)
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Patch

diff --git a/arch/arm/lib/semihosting.S b/arch/arm/lib/semihosting.S
index 393aade94a5..6e1691a832c 100644
--- a/arch/arm/lib/semihosting.S
+++ b/arch/arm/lib/semihosting.S
@@ -18,11 +18,17 @@  ENTRY(smh_trap)
 #elif defined(CONFIG_SYS_THUMB_BUILD)
 	svc	#0xab
 #else
+#if CONFIG_SYS_ARM_ARCH < 7
+	/* Before the ARMv7 exception model, svc (swi) clobbers lr */
+	mov	r2, lr
+#endif
 	svc	#0x123456
 #endif
 
 #if defined(CONFIG_ARM64)
 	ret
+#elif CONFIG_SYS_ARM_ARCH < 7
+	bx	r2
 #else
 	bx	lr
 #endif