| Message ID | 20231001225212.19081-1-andre.przywara@arm.com |
|---|---|
| State | Accepted |
| Commit | 3d5e52bd97f747694fac9259b4d2879a48256a7b |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | ARM: psci: move GIC address override to Kconfig | expand |
On 10/1/23 16:52, Andre Przywara wrote: > As the code to switch an ARM core from secure to the non-secure state > needs to know the base address of the Generic Interrupt Controller > (GIC), we read an Arm Cortex defined system register that is supposed to > hold that base address. However there are SoCs out there that get this > wrong, and this CBAR register either reads as 0 or points to the wrong > address. To accommodate those systems, so far we use a macro defined in > some platform specific header files, for affected boards. > > To simplify future extensions, replace that macro with a Kconfig variable > that holds this override address, and define a default value for SoCs > that need it. Hi Andre, Looks great to me. I'll update my PSCI series atop this once either this or the R528 series lands (I don't want my series to depend on *two* pending patchsets). > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com> Cheers, Sam
On Sun, Oct 01, 2023 at 11:52:12PM +0100, Andre Przywara wrote: > As the code to switch an ARM core from secure to the non-secure state > needs to know the base address of the Generic Interrupt Controller > (GIC), we read an Arm Cortex defined system register that is supposed to > hold that base address. However there are SoCs out there that get this > wrong, and this CBAR register either reads as 0 or points to the wrong > address. To accommodate those systems, so far we use a macro defined in > some platform specific header files, for affected boards. > > To simplify future extensions, replace that macro with a Kconfig variable > that holds this override address, and define a default value for SoCs > that need it. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > Reviewed-by: Sam Edwards <CFSworks@gmail.com> Applied to u-boot/master, thanks!
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index ccc2f208677..f015d133cb0 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -58,6 +58,16 @@ config ARMV7_SECURE_MAX_SIZE default 0x3c00 if MACH_SUN8I && MACH_SUN8I_H3 default 0x10000 +config ARM_GIC_BASE_ADDRESS + hex + depends on ARMV7_NONSEC + depends on ARCH_EXYNOS5 + default 0x10480000 if ARCH_EXYNOS5 + help + Override the GIC base address if the Arm Cortex defined + CBAR/PERIPHBASE system register holds the wrong value. + Used by the PSCI code to configure the secure side of the GIC. + config ARMV7_VIRT bool "Enable support for hardware virtualization" if EXPERT depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 9004074da2c..bed40fa3d99 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -112,8 +112,8 @@ ENTRY(_do_nonsec_entry) ENDPROC(_do_nonsec_entry) .macro get_cbar_addr addr -#ifdef CFG_ARM_GIC_BASE_ADDRESS - ldr \addr, =CFG_ARM_GIC_BASE_ADDRESS +#ifdef CONFIG_ARM_GIC_BASE_ADDRESS + ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS #else mrc p15, 4, \addr, c15, c0, 0 @ read CBAR bfc \addr, #0, #15 @ clear reserved bits diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index c82b215b6f9..5ffeca13d91 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -26,8 +26,8 @@ static unsigned int read_id_pfr1(void) static unsigned long get_gicd_base_address(void) { -#ifdef CFG_ARM_GIC_BASE_ADDRESS - return CFG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; +#ifdef CONFIG_ARM_GIC_BASE_ADDRESS + return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; #else unsigned periphbase; diff --git a/include/configs/arndale.h b/include/configs/arndale.h index b56effcd411..fa642564f4b 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -18,7 +18,4 @@ #define CFG_SMP_PEN_ADDR 0x02020000 -/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ -#define CFG_ARM_GIC_BASE_ADDRESS 0x10480000 - #endif /* __CONFIG_H */
As the code to switch an ARM core from secure to the non-secure state needs to know the base address of the Generic Interrupt Controller (GIC), we read an Arm Cortex defined system register that is supposed to hold that base address. However there are SoCs out there that get this wrong, and this CBAR register either reads as 0 or points to the wrong address. To accommodate those systems, so far we use a macro defined in some platform specific header files, for affected boards. To simplify future extensions, replace that macro with a Kconfig variable that holds this override address, and define a default value for SoCs that need it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- Hi, this only affects the Arndale board so far, though actually the defconfig doesn't enable the non-secure and PSCI code. I keep it anyway since people could manually enable it, and we need the code for the new Allwinner T113s SoC [1]. Cheers, Andre [1] https://lore.kernel.org/u-boot/20230930183424.806520-1-CFSworks@gmail.com/T/#t arch/arm/cpu/armv7/Kconfig | 10 ++++++++++ arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- arch/arm/cpu/armv7/virt-v7.c | 4 ++-- include/configs/arndale.h | 3 --- 4 files changed, 14 insertions(+), 7 deletions(-)