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Fri, 15 Sep 2023 09:01:39 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong , Peng Fan , Jaehoon Chung Cc: Jerome Brunet , u-boot-amlogic@groups.io, u-boot@lists.denx.de Subject: [RFT PATCH 2/2] mmc: meson-gx: set 270 core phase during the identification Date: Fri, 15 Sep 2023 18:01:30 +0200 Message-Id: <20230915160130.352099-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230915160130.352099-1-jbrunet@baylibre.com> References: <20230915160130.352099-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-Patchwork-Bot: notify X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean It has been reported that some devices have problems with a 180 degree core phase. Setting 270 helped some of these devices. Other continue to struggle (while it works fine with 180 in Linux ... :sigh:) Poking around the HW, it seems that setting a 270 core phase during the identification, then using 180 for the rest of the operations, helps the device operate correctly. Signed-off-by: Jerome Brunet --- drivers/mmc/meson_gx_mmc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index c6168792cbae..284be2b9dca4 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -54,9 +54,14 @@ static void meson_mmc_config_clock(struct mmc *mmc) /* Clk always on */ meson_mmc_clk |= pdata->version->clk_always_on; - meson_mmc_clk |= CLK_CO_PHASE_180; meson_mmc_clk |= CLK_TX_PHASE_000; + /* Core phase according to mode */ + if (mmc->selected_mode == MMC_LEGACY) + meson_mmc_clk |= CLK_CO_PHASE_270; + else + meson_mmc_clk |= CLK_CO_PHASE_180; + /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ if (mmc->clock > 16000000) { clk = SD_EMMC_CLKSRC_DIV2;