Message ID | 20230814160533.D5AE068AFE@verein.lst.de |
---|---|
State | Accepted |
Commit | 6164d86984cb6246680e5d94d9ec0633f2b70e98 |
Delegated to: | Andes |
Headers | show |
Series | riscv: jh7110: visionfive2: fix u-boot crash due to missing timer | expand |
On Mon, Aug 14, 2023 at 06:05:33PM +0200, Torsten Duwe wrote: > The JH7110 has the arhitectural CPU timer on all 5 rv64 cores. > Note that in the device tree. > > Signed-off-by: Torsten Duwe <duwe@suse.de> > --- > arch/riscv/dts/jh7110.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 081b833331..ec237a46ff 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -163,6 +163,15 @@ }; }; + timer { + compatible = "riscv,timer"; + interrupts-extended = <&cpu0_intc 5>, + <&cpu1_intc 5>, + <&cpu2_intc 5>, + <&cpu3_intc 5>, + <&cpu4_intc 5>; + }; + osc: oscillator { compatible = "fixed-clock"; clock-output-names = "osc";
The JH7110 has the arhitectural CPU timer on all 5 rv64 cores. Note that in the device tree. Signed-off-by: Torsten Duwe <duwe@suse.de> --- arch/riscv/dts/jh7110.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)