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Thu, 03 Aug 2023 04:08:43 -0700 (PDT) Received: from pegmas-T15.fritz.box ([151.71.248.167]) by smtp.gmail.com with ESMTPSA id e3-20020a17090681c300b00997d76981e0sm10329528ejx.208.2023.08.03.04.08.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 04:08:42 -0700 (PDT) From: Massimo Pegorer To: u-boot@lists.denx.de, Simon Glass , Philipp Tomsich , Kever Yang , Akash Gajjar Cc: Lukasz Majewski , Sean Anderson , Massimo Pegorer Subject: [PATCH 3/3] dts: rockchip: rk3308: Avoid warning for serial probe on prereloc Date: Thu, 3 Aug 2023 13:08:13 +0200 Message-Id: <20230803110813.175956-4-massimo.pegorer+oss@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230803110813.175956-1-massimo.pegorer+oss@gmail.com> References: <20230803110813.175956-1-massimo.pegorer+oss@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 03 Aug 2023 13:09:10 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Make device tree complete and consistent for pre relocation phase. Some nodes are missing, causing warnings to be issued on serial port probing during pre relocation phase (uclass_get_device_by_phandle_id fails when called by pinctrl_select_state_full: none of these failures is fatal nor causing issues). Add to *-u-boot.dtsi all required nodes with the 'bootph-some-ram' attribute. Signed-off-by: Massimo Pegorer Reviewed-by: Kever Yang --- arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index 61415559b7..d88dee8057 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -13,3 +13,30 @@ &uart0 { bootph-all; }; + +&pinctrl { + bootph-some-ram; + + uart0 { + bootph-some-ram; + }; + rtc { + bootph-some-ram; + }; +}; + +&uart0_xfer { + bootph-some-ram; +}; + +&uart0_cts { + bootph-some-ram; +}; + +&uart0_rts { + bootph-some-ram; +}; + +&rtc_32k { + bootph-some-ram; +};