From patchwork Tue Jul 25 08:08:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?S=C3=A9bastien_Szymanski?= X-Patchwork-Id: 1812306 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R9BCB2ql8z1yYc for ; Tue, 25 Jul 2023 19:13:10 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8CDE386926; Tue, 25 Jul 2023 11:13:07 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=armadeus.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id A001B86909; Tue, 25 Jul 2023 11:10:41 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from 5.mo560.mail-out.ovh.net (5.mo560.mail-out.ovh.net [87.98.181.248]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C03A786846 for ; Tue, 25 Jul 2023 11:08:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=armadeus.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sebastien.szymanski@armadeus.com Received: from director7.ghost.mail-out.ovh.net (unknown [10.109.146.131]) by mo560.mail-out.ovh.net (Postfix) with ESMTP id 6DFA127285 for ; Tue, 25 Jul 2023 08:09:28 +0000 (UTC) Received: from ghost-submission-6684bf9d7b-4qszx (unknown [10.110.208.100]) by director7.ghost.mail-out.ovh.net (Postfix) with ESMTPS id BE6D81FEB0; Tue, 25 Jul 2023 08:09:27 +0000 (UTC) Received: from armadeus.com ([37.59.142.105]) by ghost-submission-6684bf9d7b-4qszx with ESMTPSA id 6MunKzeDv2S7ODkA6AgW7A (envelope-from ); Tue, 25 Jul 2023 08:09:27 +0000 Authentication-Results: garm.ovh; auth=pass (GARM-105G00693c12f87-593e-402f-91f4-c24b170a0e8d, A2A62B8317AF7ADE30A548E36DF2B69896D5794A) smtp.auth=sebastien.szymanski@armadeus.com X-OVh-ClientIp: 92.148.253.243 From: =?utf-8?q?S=C3=A9bastien_Szymanski?= To: u-boot@lists.denx.de Cc: Stefano Babic , Fabio Estevam , "NXP i . MX U-Boot Team" , Peng Fan , Lukasz Majewski , Sean Anderson , Ye Li , Alice Guo , =?utf-8?q?S=C3=A9bast?= =?utf-8?q?ien_Szymanski?= Subject: [PATCH 3/4] serial: lpuart: Enable IPG clock Date: Tue, 25 Jul 2023 10:08:55 +0200 Message-ID: <20230725080856.26567-4-sebastien.szymanski@armadeus.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230725080856.26567-1-sebastien.szymanski@armadeus.com> References: <20230725080856.26567-1-sebastien.szymanski@armadeus.com> MIME-Version: 1.0 X-Ovh-Tracer-Id: 9455307420702469099 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedviedriedtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvvefufffkofgjfhggtgfgsehtkeertdertdejnecuhfhrohhmpefurogsrghsthhivghnucfuiiihmhgrnhhskhhiuceoshgvsggrshhtihgvnhdrshiihihmrghnshhkihesrghrmhgruggvuhhsrdgtohhmqeenucggtffrrghtthgvrhhnpeefleekfeehkedvueevieetudfhgeelhffgffdvffefleevveevieduveetfedvheenucffohhmrghinhepghhithhhuhgsrdgtohhmnecukfhppeduvdejrddtrddtrddupdelvddrudegkedrvdehfedrvdegfedpfeejrdehledrudegvddruddtheenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpeduvdejrddtrddtrddupdhmrghilhhfrhhomhepoehsvggsrghsthhivghnrdhsiiihmhgrnhhskhhisegrrhhmrgguvghushdrtghomheqpdhnsggprhgtphhtthhopedupdhrtghpthhtohepuhdqsghoohhtsehlihhsthhsrdguvghngidruggvpdfovfetjfhoshhtpehmohehiedtpdhmohguvgepshhmthhpohhuth X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Ye Li Current codes only ennable the PER clock. However on iMX8 the LPUART also needs IPG clock which is an LPCG. Should not depend on the default LPCG setting. Signed-off-by: Ye Li Reviewed-by: Peng Fan Signed-off-by: Sébastien Szymanski --- This commit comes from downstream U-Boot: https://github.com/nxp-imx/uboot-imx/commit/16aa73211a260c6f04d489ff8aa3476c670a7022 drivers/serial/serial_lpuart.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 51e66abdbc15..ce08a6b4486c 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -480,18 +480,30 @@ static int lpuart_serial_probe(struct udevice *dev) { #if CONFIG_IS_ENABLED(CLK) struct clk per_clk; + struct clk ipg_clk; int ret; ret = clk_get_by_name(dev, "per", &per_clk); if (!ret) { ret = clk_enable(&per_clk); if (ret) { - dev_err(dev, "Failed to get per clk: %d\n", ret); + dev_err(dev, "Failed to enable per clk: %d\n", ret); return ret; } } else { debug("%s: Failed to get per clk: %d\n", __func__, ret); } + + ret = clk_get_by_name(dev, "ipg", &ipg_clk); + if (!ret) { + ret = clk_enable(&ipg_clk); + if (ret) { + dev_err(dev, "Failed to enable ipg clk: %d\n", ret); + return ret; + } + } else { + debug("%s: Failed to get ipg clk: %d\n", __func__, ret); + } #endif if (is_lpuart32(dev))