Message ID | 20230707105011.129241-3-hal.feng@starfivetech.com |
---|---|
State | Accepted |
Commit | 005f9627d02e8ecab3c58c77889060e72f7fa25d |
Delegated to: | Andes |
Headers | show |
Series | Make the clock dt-bindings and DT nodes consistent with Linux | expand |
On Fri, Jul 07, 2023 at 06:50:08PM +0800, Hal Feng wrote: > From: Xingyu Wu <xingyu.wu@starfivetech.com> > > Add child node about PLL clock controller in sys_syscon node. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > --- > arch/riscv/dts/jh7110.dtsi | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index bd60879615..3e5bddccc5 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -491,8 +491,14 @@ }; sys_syscon: sys_syscon@13030000 { - compatible = "starfive,jh7110-sys-syscon","syscon"; + compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd"; reg = <0x0 0x13030000 0x0 0x1000>; + + pllclk: clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; }; sysgpio: pinctrl@13040000 {