@@ -313,9 +313,9 @@
<&syscrg JH7110_SYSCLK_BUS_ROOT>,
<&syscrg JH7110_SYSCLK_PERH_ROOT>,
<&syscrg JH7110_SYSCLK_QSPI_REF>;
- assigned-clock-parents = <&syscrg JH7110_SYSCLK_PLL0_OUT>,
- <&syscrg JH7110_SYSCLK_PLL2_OUT>,
- <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+ assigned-clock-parents = <&sys_syscon JH7110_SYSCLK_PLL0_OUT>,
+ <&sys_syscon JH7110_SYSCLK_PLL2_OUT>,
+ <&sys_syscon JH7110_SYSCLK_PLL2_OUT>,
<&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
assigned-clock-rates = <0>, <0>, <0>, <0>;
};
@@ -500,6 +500,7 @@
sys_syscon: sys_syscon@13030000 {
compatible = "starfive,jh7110-sys-syscon","syscon";
reg = <0x0 0x13030000 0x0 0x1000>;
+ #clock-cells = <1>;
};
sysgpio: pinctrl@13040000 {
@@ -11,6 +11,7 @@
#include <clk-uclass.h>
#include <div64.h>
#include <dm/device.h>
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
@@ -286,7 +287,10 @@ struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
if (!pll_clk || !base || !sysreg)
return ERR_PTR(-EINVAL);
-
+#ifdef DEBUG
+ printf("pll: %s - %s base: %p sysreg: %p\n",
+ parent_name, name, base, sysreg);
+#endif
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll)
return ERR_PTR(-ENOMEM);
@@ -314,8 +318,36 @@ struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
return clk;
}
+static int jh7110_pllclk_probe(struct udevice *dev)
+{
+ void __iomem *addr, *reg;
+
+ /* TODO: get below address(es) from OF DT! */
+ addr = (void __iomem *)0x13030000;
+ reg = (void __iomem *)0x13020000;
+
+ clk_dm(JH7110_SYSCLK_PLL0_OUT,
+ starfive_jh7110_pll("pll0_out", "oscillator", (void __iomem *)addr,
+ reg, &starfive_jh7110_pll0));
+ clk_dm(JH7110_SYSCLK_PLL1_OUT,
+ starfive_jh7110_pll("pll1_out", "oscillator", (void __iomem *)addr,
+ reg, &starfive_jh7110_pll1));
+ clk_dm(JH7110_SYSCLK_PLL2_OUT,
+ starfive_jh7110_pll("pll2_out", "oscillator", (void __iomem *)addr,
+ reg, &starfive_jh7110_pll2));
+ return 0;
+}
+
+static const struct udevice_id jh7110_pllclk_of_match[] = {
+ { .compatible = "starfive,jh7110-sys-syscon" },
+ { }
+};
+
U_BOOT_DRIVER(jh7110_clk_pllx) = {
.name = UBOOT_DM_CLK_JH7110_PLLX,
.id = UCLASS_CLK,
+ .of_match = jh7110_pllclk_of_match,
.ops = &clk_jh7110_ops,
+ .probe = jh7110_pllclk_probe,
};
+
@@ -246,9 +246,11 @@ static int jh7110_syscrg_init(struct udevice *dev)
clk_dm(JH7110_SYSCLK_PLL0_OUT,
starfive_jh7110_pll("pll0_out", "oscillator", (void __iomem *)addr,
priv->reg, &starfive_jh7110_pll0));
+#if 0
clk_dm(JH7110_SYSCLK_PLL1_OUT,
starfive_jh7110_pll("pll1_out", "oscillator", (void __iomem *)addr,
priv->reg, &starfive_jh7110_pll1));
+#endif
clk_dm(JH7110_SYSCLK_PLL2_OUT,
starfive_jh7110_pll("pll2_out", "oscillator", (void __iomem *)addr,
priv->reg, &starfive_jh7110_pll2));
@@ -436,7 +436,7 @@ int dm_init_and_scan(bool pre_reloc_only)
return ret;
}
}
- if (CONFIG_IS_ENABLED(DM_EVENT) && !(gd->flags & GD_FLG_RELOC)) {
+ if (CONFIG_IS_ENABLED(DM_EVENT) /* && !(gd->flags & GD_FLG_RELOC) */ ) {
ret = event_notify_null(EVT_DM_POST_INIT_F);
if (ret)
return log_msg_ret("ev", ret);
@@ -199,9 +199,9 @@
#define JH7110_SYSCLK_TDM_CLK_TDM_N 188
#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
-#define JH7110_SYSCLK_PLL0_OUT 190
-#define JH7110_SYSCLK_PLL1_OUT 191
-#define JH7110_SYSCLK_PLL2_OUT 192
+#define JH7110_SYSCLK_PLL0_OUT 0
+#define JH7110_SYSCLK_PLL1_OUT 1
+#define JH7110_SYSCLK_PLL2_OUT 2
#define JH7110_SYSCLK_END 193