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[198.54.134.172]) by smtp.gmail.com with ESMTPSA id jc12-20020a17090325cc00b001aaef9d0102sm664595plb.197.2023.05.27.17.10.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 May 2023 17:10:13 -0700 (PDT) From: Sam Edwards X-Google-Original-From: Sam Edwards To: u-boot@lists.denx.de Cc: Tom Rini , Sam Edwards Subject: [PATCH] psci: fix use of clobbered registers in asm Date: Sat, 27 May 2023 18:09:42 -0600 Message-Id: <20230528000942.231907-1-CFSworks@gmail.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The functions `psci_get_context_id` and `psci_get_target_pc` are written in C, so the C compiler may clobber registers r0-r3. Do not use these registers to save data across calls. Signed-off-by: Sam Edwards --- arch/arm/cpu/armv7/psci.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 6c066e50d9..41428728b7 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -311,11 +311,11 @@ ENTRY(psci_cpu_entry) bl psci_arch_cpu_entry bl psci_get_cpu_id @ CPU ID => r0 - mov r2, r0 @ CPU ID => r2 bl psci_get_context_id @ context id => r0 - mov r1, r0 @ context id => r1 - mov r0, r2 @ CPU ID => r0 + push {r0} @ save context id + bl psci_get_cpu_id @ CPU ID => r0 bl psci_get_target_pc @ target PC => r0 + pop {r1} @ context id => r1 b _do_nonsec_entry ENDPROC(psci_cpu_entry)