From patchwork Thu May 18 06:41:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yanhong Wang X-Patchwork-Id: 1783043 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QML3R3dr0z20dn for ; Thu, 18 May 2023 16:41:23 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D856484A00; Thu, 18 May 2023 08:41:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id C3A6584D10; Thu, 18 May 2023 08:41:18 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by phobos.denx.de (Postfix) with ESMTP id C2933847B8 for ; Thu, 18 May 2023 08:41:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=yanhong.wang@starfivetech.com Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 1616B7FDC; Thu, 18 May 2023 14:41:11 +0800 (CST) Received: from EXMBX173.cuchost.com (172.16.6.93) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 18 May 2023 14:41:10 +0800 Received: from wyh-VirtualBox.starfivetech.com (171.223.208.138) by EXMBX173.cuchost.com (172.16.6.93) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 18 May 2023 14:41:10 +0800 From: Yanhong Wang To: , Rick Chen , Leo CC: Bo Gan , Sean Anderson , "Lukasz Majewski" , "samin . guo" , "Yanhong Wang" Subject: [PATCH v1 1/2] arch: riscv: jh7110: Split the zeroing of L2 LIM on JH7110 Date: Thu, 18 May 2023 14:41:05 +0800 Message-ID: <20230518064106.9082-1-yanhong.wang@starfivetech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX173.cuchost.com (172.16.6.93) X-YovoleRuleAgent: yovoleflag X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The per-hart stack,malloc space and global variable 'gd' sits between __bss_end and L2_LIM_MEM_END.Zeroing this region could overwrite the hart's stack, and other harts' stacks.If it were to save and restore `ra` register, then we would crash in function epilogue. Also, we are having data-races here, because harts are writing over each other's stack. So we should split the zeroing of L2 LIM into different places just before the region is to be used. For stacks,let each hart clearing its own stack, and for the malloc space, we can do so during malloc initialization. The global variable 'gd' is initialized in the board_init_f_init_reserve function. Signed-off-by: Yanhong Wang --- arch/riscv/cpu/jh7110/spl.c | 6 +++--- arch/riscv/cpu/start.S | 14 ++++++++++++++ common/init/board_init.c | 1 + 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index 104f0fe949..6a48fba63d 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -10,7 +10,6 @@ #include #define CSR_U74_FEATURE_DISABLE 0x7c1 -#define L2_LIM_MEM_END 0x81FFFFFUL int spl_soc_init(void) { @@ -42,13 +41,14 @@ void harts_early_init(void) csr_write(CSR_U74_FEATURE_DISABLE, 0); /* clear L2 LIM memory - * set __bss_end to 0x81FFFFF region to zero + * set __bss_end to stack end region to zero * The L2 Cache Controller supports ECC. ECC is applied to SRAM. * If it is not cleared, the ECC part is invalid, and an ECC error * will be reported when reading data. */ ptr = (ulong *)&__bss_end; - len = L2_LIM_MEM_END - (ulong)&__bss_end; + len = CONFIG_SPL_STACK - CONFIG_VAL(SYS_MALLOC_F_LEN) - sizeof(*gd) - + CONFIG_NR_CPUS * BIT(CONFIG_STACK_SIZE_SHIFT) - (ulong)&__bss_end; remain = len % sizeof(ulong); len /= sizeof(ulong); diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index dad22bfea8..46da9ec503 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -118,6 +118,20 @@ call_board_init_f_0: mv sp, a0 #endif +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) && \ + defined(CONFIG_STARFIVE_JH7110) + + /* Set the stack region to zero */ + li t0, 1 + slli t1, t0, CONFIG_STACK_SIZE_SHIFT + mv t0, sp + sub t1, t0, t1 +clear_stack: + SREG zero, 0(t1) + addi t1, t1, REGBYTES + blt t1, t0, clear_stack +#endif + /* Configure proprietary settings and customized CSRs of harts */ call_harts_early_init: jal harts_early_init diff --git a/common/init/board_init.c b/common/init/board_init.c index 96ffb79a98..46e4e4abc7 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -162,6 +162,7 @@ void board_init_f_init_reserve(ulong base) #if CONFIG_VAL(SYS_MALLOC_F_LEN) /* go down one 'early malloc arena' */ gd->malloc_base = base; + memset((void *)base, 0, CONFIG_VAL(SYS_MALLOC_F_LEN)); #endif if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))