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Wed, 12 Apr 2023 03:39:56 -0400 (EDT) From: Mathew McBride To: u-boot@lists.denx.de, Ioana Ciornei , Peng Fan , Gaurav Jain Cc: Mathew McBride Subject: [PATCH 06/18] arm: dts: fsl-ls1088a: import and sync full SMMU nodes with Linux Date: Wed, 12 Apr 2023 07:38:18 +0000 Message-Id: <20230412073830.13928-7-matt@traverse.com.au> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20230412073830.13928-1-matt@traverse.com.au> References: <20230412073830.13928-1-matt@traverse.com.au> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean To synchronise the device tree in U-Boot with Linux, the GIC (Interrupt Controller) and SMMU/IOMMU nodes need to be synchronised before changing any dependent components like PCIe and DPAA2/fsl-mc. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan --- arch/arm/dts/fsl-ls1088a.dtsi | 109 +++++++++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 3afd847baf..05da798380 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -15,11 +15,23 @@ gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ #interrupt-cells = <3>; interrupt-controller; - interrupts = <1 9 0x4>; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ + <0x0 0x0c0c0000 0 0x2000>, /* GICC */ + <0x0 0x0c0d0000 0 0x1000>, /* GICH */ + <0x0 0x0c0e0000 0 0x20000>; /* GICV */ + interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its: gic-its@6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; }; timer { @@ -68,6 +80,97 @@ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; + + smmu: iommu@5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #iommu-cells = <1>; + stream-match-mask = <0x7C00>; + dma-coherent; + #global-interrupts = <12>; + // global secure fault + interrupts = , + // combined secure + , + // global non-secure fault + , + // combined non-secure + , + // performance counter interrupts 0-7 + , + , + , + , + , + , + , + , + // per context interrupt, 64 interrupts + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; }; i2c0: i2c@2000000 {