diff mbox series

[09/18] arm: dts: fsl-ls1088a: import CPU definition from Linux kernel

Message ID 20230412073830.13928-10-matt@traverse.com.au
State Accepted
Commit 2d6fce16c6dff419bfdd0e8c4cf257723bcb4d79
Delegated to: Peng Fan
Headers show
Series Synchronise LS1088A/Ten64 device tree with Linux | expand

Commit Message

Mathew McBride April 12, 2023, 7:38 a.m. UTC 
This is required for Linux to boot using the same FDT as
U-Boot (such as passing the control FDT to bootefi).

Signed-off-by: Mathew McBride <matt@traverse.com.au>
---
 arch/arm/dts/fsl-ls1088a.dtsi | 87 +++++++++++++++++++++++++++++++++++
 1 file changed, 87 insertions(+)

Comments

Peng Fan (OSS) April 28, 2023, 3:28 a.m. UTC | #1 
On 4/12/2023 3:38 PM, Mathew McBride wrote:
> This is required for Linux to boot using the same FDT as
> U-Boot (such as passing the control FDT to bootefi).
> 
> Signed-off-by: Mathew McBride<matt@traverse.com.au>

Reviewed-by: Peng Fan <peng.fan@nxp.com>
diff mbox series

Patch

diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 85316ddb66..dc6241e20d 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -13,6 +13,93 @@ 
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* We have 2 clusters having 4 Cortex-A53 cores each */
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x2>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x3>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu4: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x100>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu5: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x101>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu6: cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x102>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		cpu7: cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x103>;
+			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
+			cpu-idle-states = <&CPU_PH20>;
+			#cooling-cells = <2>;
+		};
+
+		CPU_PH20: cpu-ph20 {
+			compatible = "arm,idle-state";
+			idle-state-name = "PH20";
+			arm,psci-suspend-param = <0x0>;
+			entry-latency-us = <1000>;
+			exit-latency-us = <1000>;
+			min-residency-us = <3000>;
+		};
+	};
+
 	gic: interrupt-controller@6000000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <3>;