diff mbox series

[v5,15/17] riscv: dts: jh7110: Add initial u-boot device tree

Message ID 20230329034224.26545-16-yanhong.wang@starfivetech.com
State Accepted
Delegated to: Andes
Headers show
Series Basic StarFive JH7110 RISC-V SoC support | expand

Commit Message

Yanhong Wang March 29, 2023, 3:42 a.m. UTC 
Add initial u-boot device tree for the JH7110 RISC-V SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/dts/jh7110-u-boot.dtsi | 99 +++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)
 create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi

Comments

Leo Liang April 20, 2023, 6:33 p.m. UTC | #1 
Hi YanHong,

On Wed, Mar 29, 2023 at 11:42:22AM +0800, Yanhong Wang wrote:
> Add initial u-boot device tree for the JH7110 RISC-V SoC.
> 
> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
> Tested-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/dts/jh7110-u-boot.dtsi | 99 +++++++++++++++++++++++++++++++
>  1 file changed, 99 insertions(+)
>  create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi
> 
> diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
> new file mode 100644
> index 0000000000..31ca054f54
> --- /dev/null
> +++ b/arch/riscv/dts/jh7110-u-boot.dtsi
> @@ -0,0 +1,99 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
> +
> +/ {
> +	cpus: cpus {
> +		u-boot,dm-spl;

u-boot,dm-spl tag is replaced by bootph-pre-ram in this patch set.
7703efbc99 ("dm: Move to new driver model schema for device tree tags")
(https://patchwork.ozlabs.org/project/uboot/list/?series=341679&archive=both&state=*)

I have modified all the u-boot,dm-spl tag to bootph-pre-ram 
in all the dts you introduced when merging the patch set,
so you don't have to respin the patch set again.
Just sending this mail to keep you informed.

Best regards,
Leo
diff mbox series

Patch

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
new file mode 100644
index 0000000000..31ca054f54
--- /dev/null
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -0,0 +1,99 @@ 
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+/ {
+	cpus: cpus {
+		u-boot,dm-spl;
+
+		S7_0: cpu@0 {
+			u-boot,dm-spl;
+			status = "okay";
+			cpu0_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+
+		U74_1: cpu@1 {
+			u-boot,dm-spl;
+			cpu1_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+
+		U74_2: cpu@2 {
+			u-boot,dm-spl;
+			cpu2_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+
+		U74_3: cpu@3 {
+			u-boot,dm-spl;
+			cpu3_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+
+		U74_4: cpu@4 {
+			u-boot,dm-spl;
+			cpu4_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+	};
+
+	soc {
+		u-boot,dm-spl;
+
+		clint: timer@2000000 {
+			u-boot,dm-spl;
+		};
+
+		dmc: dmc@15700000 {
+			u-boot,dm-spl;
+			compatible = "starfive,jh7110-dmc";
+			reg = <0x0 0x15700000 0x0 0x10000>,
+				<0x0 0x13000000 0x0 0x10000>;
+			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+				<&syscrg JH7110_SYSRST_DDR_OSC>,
+				<&syscrg JH7110_SYSRST_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
+			clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>;
+			clock-names = "pll1_out";
+			clock-frequency = <2133>;
+		};
+	};
+};
+
+&osc {
+	u-boot,dm-spl;
+};
+
+&gmac0_rmii_refin {
+	u-boot,dm-spl;
+};
+
+&aoncrg {
+	u-boot,dm-spl;
+};
+
+&syscrg {
+	u-boot,dm-spl;
+	starfive,sys-syscon = <&sys_syscon>;
+};
+
+&stgcrg {
+	u-boot,dm-spl;
+};
+
+&sys_syscon {
+	u-boot,dm-spl;
+};
+
+&S7_0 {
+	status = "okay";
+};