Message ID | 20230314003755.512696-10-jonas@kwiboo.se |
---|---|
State | Accepted |
Commit | d11f0dac30215361aa046f593d003a7ea094e8a1 |
Delegated to: | Kever Yang |
Headers | show |
Series | rockchip: Fixes for RK3568 and RK3588 and cleanup | expand |
On 2023/3/14 08:38, Jonas Karlman wrote: > The get_mmc_clk ops is expected to set a clock rate and return the > configured rate as an unsigned value. However, if clk_set_rate fails, > e.g. using a fixed rate clock, a negative error value is returned. > > The mmc core will treat this as a valid unsigned rate and tries to > configure a divider based on this bogus clock rate. > > Use 0 as the return value when setting clock rate fails, the mmc core > will configure to use bypass mode instead of using a bogus divider. > > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > drivers/mmc/rockchip_dw_mmc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c > index 3661ce33143e..72c820ee6330 100644 > --- a/drivers/mmc/rockchip_dw_mmc.c > +++ b/drivers/mmc/rockchip_dw_mmc.c > @@ -52,7 +52,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) > ret = clk_set_rate(&priv->clk, freq); > if (ret < 0) { > debug("%s: err=%d\n", __func__, ret); > - return ret; > + return 0; > } > > return freq;
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 3661ce33143e..72c820ee6330 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -52,7 +52,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) ret = clk_set_rate(&priv->clk, freq); if (ret < 0) { debug("%s: err=%d\n", __func__, ret); - return ret; + return 0; } return freq;
The get_mmc_clk ops is expected to set a clock rate and return the configured rate as an unsigned value. However, if clk_set_rate fails, e.g. using a fixed rate clock, a negative error value is returned. The mmc core will treat this as a valid unsigned rate and tries to configure a divider based on this bogus clock rate. Use 0 as the return value when setting clock rate fails, the mmc core will configure to use bypass mode instead of using a bogus divider. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- drivers/mmc/rockchip_dw_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)