From patchwork Wed Jan 18 08:11:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yanhong Wang X-Patchwork-Id: 1728053 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NxdmM1pCdz23fT for ; Wed, 18 Jan 2023 19:12:51 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 276FE85615; Wed, 18 Jan 2023 09:11:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8731E8565F; Wed, 18 Jan 2023 09:11:44 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by phobos.denx.de (Postfix) with ESMTP id DCB69855CF for ; Wed, 18 Jan 2023 09:11:36 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=yanhong.wang@starfivetech.com Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id AB7FF24E1BB; Wed, 18 Jan 2023 16:11:34 +0800 (CST) Received: from EXMBX073.cuchost.com (172.16.6.83) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 18 Jan 2023 16:11:34 +0800 Received: from wyh-VirtualBox.starfivetech.com (171.223.208.138) by EXMBX073.cuchost.com (172.16.6.83) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 18 Jan 2023 16:11:33 +0800 From: Yanhong Wang To: , Rick Chen , Leo , Lukasz Majewski , Sean Anderson CC: Lee Kuan Lim , Jianlong Huang , Emil Renner Berthing , Yanhong Wang Subject: [PATCH v2 01/17] riscv: cpu: jh7110: Add support for jh7110 SoC Date: Wed, 18 Jan 2023 16:11:16 +0800 Message-ID: <20230118081132.31403-2-yanhong.wang@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230118081132.31403-1-yanhong.wang@starfivetech.com> References: <20230118081132.31403-1-yanhong.wang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX073.cuchost.com (172.16.6.83) X-YovoleRuleAgent: yovoleflag X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Add StarFive JH7110 SoC to support RISC-V arch. Signed-off-by: Yanhong Wang Reviewed-by: Rick Chen --- arch/riscv/cpu/jh7110/Makefile | 10 ++++ arch/riscv/cpu/jh7110/cpu.c | 23 ++++++++ arch/riscv/cpu/jh7110/dram.c | 38 ++++++++++++++ arch/riscv/cpu/jh7110/spl.c | 64 +++++++++++++++++++++++ arch/riscv/include/asm/arch-jh7110/regs.h | 19 +++++++ arch/riscv/include/asm/arch-jh7110/spl.h | 12 +++++ 6 files changed, 166 insertions(+) create mode 100644 arch/riscv/cpu/jh7110/Makefile create mode 100644 arch/riscv/cpu/jh7110/cpu.c create mode 100644 arch/riscv/cpu/jh7110/dram.c create mode 100644 arch/riscv/cpu/jh7110/spl.c create mode 100644 arch/riscv/include/asm/arch-jh7110/regs.h create mode 100644 arch/riscv/include/asm/arch-jh7110/spl.h diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile new file mode 100644 index 0000000000..951c95631e --- /dev/null +++ b/arch/riscv/cpu/jh7110/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive Technology Co., Ltd. + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y += spl.o +else +obj-y += cpu.o +obj-y += dram.o +endif diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c new file mode 100644 index 0000000000..1d7c026584 --- /dev/null +++ b/arch/riscv/cpu/jh7110/cpu.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + */ + +#include +#include + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c new file mode 100644 index 0000000000..2ad3f2044a --- /dev/null +++ b/arch/riscv/cpu/jh7110/dram.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +phys_size_t board_get_usable_ram_top(phys_size_t total_size) +{ + /* + * Ensure that we run from first 4GB so that all + * addresses used by U-Boot are 32bit addresses. + * + * This in-turn ensures that 32bit DMA capable + * devices work fine because DMA mapping APIs will + * provide 32bit DMA addresses only. + */ + if (IS_ENABLED(CONFIG_64BIT) && gd->ram_top > SZ_4G) + return SZ_4G; + + return gd->ram_top; +} diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c new file mode 100644 index 0000000000..104f0fe949 --- /dev/null +++ b/arch/riscv/cpu/jh7110/spl.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + */ + +#include +#include +#include +#include + +#define CSR_U74_FEATURE_DISABLE 0x7c1 +#define L2_LIM_MEM_END 0x81FFFFFUL + +int spl_soc_init(void) +{ + int ret; + struct udevice *dev; + + /* DDR init */ + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + return 0; +} + +void harts_early_init(void) +{ + ulong *ptr; + u8 *tmp; + ulong len, remain; + /* + * Feature Disable CSR + * + * Clear feature disable CSR to '0' to turn on all features for + * each core. This operation must be in M-mode. + */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) + csr_write(CSR_U74_FEATURE_DISABLE, 0); + + /* clear L2 LIM memory + * set __bss_end to 0x81FFFFF region to zero + * The L2 Cache Controller supports ECC. ECC is applied to SRAM. + * If it is not cleared, the ECC part is invalid, and an ECC error + * will be reported when reading data. + */ + ptr = (ulong *)&__bss_end; + len = L2_LIM_MEM_END - (ulong)&__bss_end; + remain = len % sizeof(ulong); + len /= sizeof(ulong); + + while (len--) + *ptr++ = 0; + + /* clear the remain bytes */ + if (remain) { + tmp = (u8 *)ptr; + while (remain--) + *tmp++ = 0; + } +} diff --git a/arch/riscv/include/asm/arch-jh7110/regs.h b/arch/riscv/include/asm/arch-jh7110/regs.h new file mode 100644 index 0000000000..05026870a0 --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7110/regs.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + */ + +#ifndef __STARFIVE_JH7110_REGS_H +#define __STARFIVE_JH7110_REGS_H + +#define JH7110_SYS_CRG 0x13020000 +#define JH7110_SYS_SYSCON 0x13030000 +#define JH7110_SYS_IOMUX 0x13040000 +#define JH7110_AON_CRG 0x17000000 +#define JH7110_AON_SYSCON 0x17010000 + +#define JH7110_BOOT_MODE_SELECT_REG 0x1702002c +#define JH7110_BOOT_MODE_SELECT_MASK GENMASK(1, 0) + +#endif /* __STARFIVE_JH7110_REGS_H */ diff --git a/arch/riscv/include/asm/arch-jh7110/spl.h b/arch/riscv/include/asm/arch-jh7110/spl.h new file mode 100644 index 0000000000..23ce8871b3 --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7110/spl.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + */ + +#ifndef _SPL_STARFIVE_H +#define _SPL_STARFIVE_H + +int spl_soc_init(void); + +#endif /* _SPL_STARFIVE_H */