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[v2,15/17] riscv: dts: jh7110: Add initial u-boot device tree

Message ID 20230118081132.31403-16-yanhong.wang@starfivetech.com
State Changes Requested
Delegated to: Andes
Headers show
Series Basic StarFive JH7110 RISC-V SoC support | expand

Commit Message

Yanhong Wang Jan. 18, 2023, 8:11 a.m. UTC 
Add initial u-boot device tree for the JH7110 RISC-V SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
---
 arch/riscv/dts/jh7110-u-boot.dtsi | 72 +++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi
diff mbox series

Patch

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
new file mode 100644
index 0000000000..a15e1c6a45
--- /dev/null
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -0,0 +1,72 @@ 
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <dt-bindings/reset/starfive-jh7110.h>
+
+/ {
+	cpus: cpus {
+		u-boot,dm-spl;
+
+		S76_0: cpu@0 {
+			u-boot,dm-spl;
+			status = "okay";
+			cpu0_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+
+		U74_1: cpu@1 {
+			u-boot,dm-spl;
+			cpu1_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+
+		U74_2: cpu@2 {
+			u-boot,dm-spl;
+			cpu2_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+
+		U74_3: cpu@3 {
+			u-boot,dm-spl;
+			cpu3_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+
+		U74_4: cpu@4 {
+			u-boot,dm-spl;
+			cpu4_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+	};
+
+	soc {
+		u-boot,dm-spl;
+
+		clint: clint@2000000 {
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&gmac0_rmii_refin {
+	u-boot,dm-spl;
+};
+
+&aoncrg {
+	u-boot,dm-spl;
+};
+
+&syscrg {
+	u-boot,dm-spl;
+};
+
+&stgcrg {
+	u-boot,dm-spl;
+};