diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS
new file mode 100644
index 0000000000..c5369086d8
--- /dev/null
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -0,0 +1,7 @@
+STARFIVE JH7110 VISIONFIVE2 BOARD
+M: startfive
+S:	Maintained
+F:	arch/riscv/include/asm/arch-jh7110/
+F:	board/starfive/visionfive2/
+F:	include/configs/starfive-visionfive2.h
+F:	configs/starfive_visionfive2_defconfig
diff --git a/board/starfive/visionfive2/Makefile b/board/starfive/visionfive2/Makefile
new file mode 100644
index 0000000000..66c854df39
--- /dev/null
+++ b/board/starfive/visionfive2/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+#
+
+obj-y	:= starfive_visionfive2.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
new file mode 100644
index 0000000000..9e14cd56af
--- /dev/null
+++ b/board/starfive/visionfive2/spl.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/arch/regs.h>
+#include <asm/arch/spl.h>
+#include <asm/io.h>
+#include <log.h>
+#include <spl.h>
+
+#define JH7110_CLK_CPU_ROOT_OFFSET		0x0U
+#define JH7110_CLK_CPU_ROOT_SHIFT		24
+#define JH7110_CLK_CPU_ROOT_MASK		GENMASK(29, 24)
+#define JH7110_CLK_BUS_ROOT_OFFSET		0x14U
+#define JH7110_CLK_BUS_ROOT_SHIFT		24
+#define JH7110_CLK_BUS_ROOT_MASK		GENMASK(29, 24)
+#define JH7110_CLK_PERH_ROOT_OFFSET		0x10U
+#define JH7110_CLK_PERH_ROOT_SHIFT		24
+#define JH7110_CLK_PERH_ROOT_MASK		GENMASK(29, 24)
+#define JH7110_CLK_NOC_BUS_STG_AXI_OFFSET	0x180U
+#define JH7110_CLK_NOC_BUS_STG_AXI_SHIFT	31
+#define JH7110_CLK_NOC_BUS_STG_AXI_MASK	BIT(31)
+#define JH7110_CLK_AON_APB_FUNC_OFFSET		0x4U
+#define JH7110_CLK_AON_APB_FUNC_SHIFT		24
+#define JH7110_CLK_AON_APB_FUNC_MASK		GENMASK(29, 24)
+#define JH7110_CLK_QSPI_REF_OFFSET		0x168U
+#define JH7110_CLK_QSPI_REF_SHIFT		24
+#define JH7110_CLK_QSPI_REF_MASK		GENMASK(29, 24)
+
+#define ASSIGNED_CLOCK_PARENTS(type, val) \
+	clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_##type##_OFFSET, \
+		JH7110_CLK_##type##_MASK, \
+		((val) << JH7110_CLK_##type##_SHIFT) & JH7110_CLK_##type##_MASK)
+
+int spl_board_init_f(void)
+{
+	int ret;
+
+	ret = spl_soc_init();
+	if (ret) {
+		debug("JH7110 SPL init failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 mode;
+
+	mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
+				& JH7110_BOOT_MODE_SELECT_MASK;
+	switch (mode) {
+	case 0:
+		return BOOT_DEVICE_SPI;
+
+	case 1:
+		return BOOT_DEVICE_MMC2;
+
+	case 2:
+		return BOOT_DEVICE_MMC1;
+
+	case 3:
+		return BOOT_DEVICE_UART;
+
+	default:
+		debug("Unsupported boot device 0x%x.\n", mode);
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	ret = spl_early_init();
+	if (ret)
+		panic("spl_early_init() failed: %d\n", ret);
+
+	riscv_cpu_setup(NULL, NULL);
+	preloader_console_init();
+
+	/* select clk_pll0 by default */
+	ASSIGNED_CLOCK_PARENTS(CPU_ROOT, 1);
+
+	/* select clk_pll2 by default */
+	ASSIGNED_CLOCK_PARENTS(BUS_ROOT, 1);
+
+	/* select clk_pll2 by default */
+	ASSIGNED_CLOCK_PARENTS(PERH_ROOT, 1);
+
+	ASSIGNED_CLOCK_PARENTS(NOC_BUS_STG_AXI, 1);
+
+	clrsetbits_le32(JH7110_AON_CRG + JH7110_CLK_AON_APB_FUNC_OFFSET,
+			JH7110_CLK_AON_APB_FUNC_MASK,
+			BIT(JH7110_CLK_AON_APB_FUNC_SHIFT));
+
+	/* select clk_pll0 by default */
+	ASSIGNED_CLOCK_PARENTS(QSPI_REF, 1);
+
+	ret = spl_board_init_f();
+	if (ret) {
+		debug("spl_board_init_f init failed: %d\n", ret);
+		return;
+	}
+}
+
+#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
+	return 0;
+}
+#endif
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
new file mode 100644
index 0000000000..57f1b6ea5d
--- /dev/null
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+#define JH7110_L2_PREFETCHER_BASE_ADDR		0x2030000
+#define JH7110_L2_PREFETCHER_HART_OFFSET	0x2000
+
+/* enable U74-mc hart1~hart4 prefetcher */
+static void enable_prefetcher(void)
+{
+	u8 hart;
+	u32 *reg;
+
+	/* JH7110 use U74MC CORE IP, it include five cores(one S7 and four U7),
+	 * but only U7 cores support prefetcher configuration
+	 */
+	for (hart = 1; hart < 5; hart++) {
+		reg = (void *)(u64)(JH7110_L2_PREFETCHER_BASE_ADDR
+					+ hart * JH7110_L2_PREFETCHER_HART_OFFSET);
+
+		mb(); /* memory barrier */
+		setbits_le32(reg, 0x1);
+		mb(); /* memory barrier */
+	}
+}
+
+int board_init(void)
+{
+	enable_prefetcher();
+
+	return 0;
+}
diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h
new file mode 100644
index 0000000000..a5fba1869b
--- /dev/null
+++ b/include/configs/starfive-visionfive2.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author:	Yanhong Wang<yanhong.wang@starfivetech.com>
+ *
+ */
+
+#ifndef _STARFIVE_VISIONFIVE2_H
+#define _STARFIVE_VISIONFIVE2_H
+
+#define RISCV_MMODE_TIMERBASE		0x2000000
+#define RISCV_MMODE_TIMER_FREQ		4000000
+
+#define RISCV_SMODE_TIMER_FREQ		4000000
+
+#define __io
+
+#endif /* _STARFIVE_VISIONFIVE2_H */
