From patchwork Wed Jan 18 08:11:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yanhong Wang X-Patchwork-Id: 1728057 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NxdnH4nGVz23fT for ; Wed, 18 Jan 2023 19:13:39 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3B7B485624; Wed, 18 Jan 2023 09:12:25 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 9090185616; Wed, 18 Jan 2023 09:11:54 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by phobos.denx.de (Postfix) with ESMTP id 054768562A for ; Wed, 18 Jan 2023 09:11:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=yanhong.wang@starfivetech.com Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 3529B24E0FC; Wed, 18 Jan 2023 16:11:40 +0800 (CST) Received: from EXMBX073.cuchost.com (172.16.6.83) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 18 Jan 2023 16:11:40 +0800 Received: from wyh-VirtualBox.starfivetech.com (171.223.208.138) by EXMBX073.cuchost.com (172.16.6.83) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 18 Jan 2023 16:11:39 +0800 From: Yanhong Wang To: , Rick Chen , Leo , Lukasz Majewski , Sean Anderson CC: Lee Kuan Lim , Jianlong Huang , Emil Renner Berthing , Yanhong Wang Subject: [PATCH v2 10/17] board: starfive: add StarFive VisionFive v2 board support Date: Wed, 18 Jan 2023 16:11:25 +0800 Message-ID: <20230118081132.31403-11-yanhong.wang@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230118081132.31403-1-yanhong.wang@starfivetech.com> References: <20230118081132.31403-1-yanhong.wang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX073.cuchost.com (172.16.6.83) X-YovoleRuleAgent: yovoleflag X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang --- board/starfive/visionfive2/MAINTAINERS | 7 ++ board/starfive/visionfive2/Makefile | 7 ++ board/starfive/visionfive2/spl.c | 118 ++++++++++++++++++ .../visionfive2/starfive_visionfive2.c | 38 ++++++ include/configs/starfive-visionfive2.h | 18 +++ 5 files changed, 188 insertions(+) create mode 100644 board/starfive/visionfive2/MAINTAINERS create mode 100644 board/starfive/visionfive2/Makefile create mode 100644 board/starfive/visionfive2/spl.c create mode 100644 board/starfive/visionfive2/starfive_visionfive2.c create mode 100644 include/configs/starfive-visionfive2.h diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS new file mode 100644 index 0000000000..c5369086d8 --- /dev/null +++ b/board/starfive/visionfive2/MAINTAINERS @@ -0,0 +1,7 @@ +STARFIVE JH7110 VISIONFIVE2 BOARD +M: startfive +S: Maintained +F: arch/riscv/include/asm/arch-jh7110/ +F: board/starfive/visionfive2/ +F: include/configs/starfive-visionfive2.h +F: configs/starfive_visionfive2_defconfig diff --git a/board/starfive/visionfive2/Makefile b/board/starfive/visionfive2/Makefile new file mode 100644 index 0000000000..66c854df39 --- /dev/null +++ b/board/starfive/visionfive2/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive Technology Co., Ltd. +# + +obj-y := starfive_visionfive2.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c new file mode 100644 index 0000000000..9e14cd56af --- /dev/null +++ b/board/starfive/visionfive2/spl.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + */ + +#include +#include +#include +#include +#include +#include + +#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U +#define JH7110_CLK_CPU_ROOT_SHIFT 24 +#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24) +#define JH7110_CLK_BUS_ROOT_OFFSET 0x14U +#define JH7110_CLK_BUS_ROOT_SHIFT 24 +#define JH7110_CLK_BUS_ROOT_MASK GENMASK(29, 24) +#define JH7110_CLK_PERH_ROOT_OFFSET 0x10U +#define JH7110_CLK_PERH_ROOT_SHIFT 24 +#define JH7110_CLK_PERH_ROOT_MASK GENMASK(29, 24) +#define JH7110_CLK_NOC_BUS_STG_AXI_OFFSET 0x180U +#define JH7110_CLK_NOC_BUS_STG_AXI_SHIFT 31 +#define JH7110_CLK_NOC_BUS_STG_AXI_MASK BIT(31) +#define JH7110_CLK_AON_APB_FUNC_OFFSET 0x4U +#define JH7110_CLK_AON_APB_FUNC_SHIFT 24 +#define JH7110_CLK_AON_APB_FUNC_MASK GENMASK(29, 24) +#define JH7110_CLK_QSPI_REF_OFFSET 0x168U +#define JH7110_CLK_QSPI_REF_SHIFT 24 +#define JH7110_CLK_QSPI_REF_MASK GENMASK(29, 24) + +#define ASSIGNED_CLOCK_PARENTS(type, val) \ + clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_##type##_OFFSET, \ + JH7110_CLK_##type##_MASK, \ + ((val) << JH7110_CLK_##type##_SHIFT) & JH7110_CLK_##type##_MASK) + +int spl_board_init_f(void) +{ + int ret; + + ret = spl_soc_init(); + if (ret) { + debug("JH7110 SPL init failed: %d\n", ret); + return ret; + } + + return 0; +} + +u32 spl_boot_device(void) +{ + u32 mode; + + mode = in_le32(JH7110_BOOT_MODE_SELECT_REG) + & JH7110_BOOT_MODE_SELECT_MASK; + switch (mode) { + case 0: + return BOOT_DEVICE_SPI; + + case 1: + return BOOT_DEVICE_MMC2; + + case 2: + return BOOT_DEVICE_MMC1; + + case 3: + return BOOT_DEVICE_UART; + + default: + debug("Unsupported boot device 0x%x.\n", mode); + return BOOT_DEVICE_NONE; + } +} + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed: %d\n", ret); + + riscv_cpu_setup(NULL, NULL); + preloader_console_init(); + + /* select clk_pll0 by default */ + ASSIGNED_CLOCK_PARENTS(CPU_ROOT, 1); + + /* select clk_pll2 by default */ + ASSIGNED_CLOCK_PARENTS(BUS_ROOT, 1); + + /* select clk_pll2 by default */ + ASSIGNED_CLOCK_PARENTS(PERH_ROOT, 1); + + ASSIGNED_CLOCK_PARENTS(NOC_BUS_STG_AXI, 1); + + clrsetbits_le32(JH7110_AON_CRG + JH7110_CLK_AON_APB_FUNC_OFFSET, + JH7110_CLK_AON_APB_FUNC_MASK, + BIT(JH7110_CLK_AON_APB_FUNC_SHIFT)); + + /* select clk_pll0 by default */ + ASSIGNED_CLOCK_PARENTS(QSPI_REF, 1); + + ret = spl_board_init_f(); + if (ret) { + debug("spl_board_init_f init failed: %d\n", ret); + return; + } +} + +#if CONFIG_IS_ENABLED(SPL_LOAD_FIT) +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c new file mode 100644 index 0000000000..57f1b6ea5d --- /dev/null +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + */ + +#include +#include +#include + +#define JH7110_L2_PREFETCHER_BASE_ADDR 0x2030000 +#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000 + +/* enable U74-mc hart1~hart4 prefetcher */ +static void enable_prefetcher(void) +{ + u8 hart; + u32 *reg; + + /* JH7110 use U74MC CORE IP, it include five cores(one S7 and four U7), + * but only U7 cores support prefetcher configuration + */ + for (hart = 1; hart < 5; hart++) { + reg = (void *)(u64)(JH7110_L2_PREFETCHER_BASE_ADDR + + hart * JH7110_L2_PREFETCHER_HART_OFFSET); + + mb(); /* memory barrier */ + setbits_le32(reg, 0x1); + mb(); /* memory barrier */ + } +} + +int board_init(void) +{ + enable_prefetcher(); + + return 0; +} diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h new file mode 100644 index 0000000000..a5fba1869b --- /dev/null +++ b/include/configs/starfive-visionfive2.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + * + */ + +#ifndef _STARFIVE_VISIONFIVE2_H +#define _STARFIVE_VISIONFIVE2_H + +#define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMER_FREQ 4000000 + +#define RISCV_SMODE_TIMER_FREQ 4000000 + +#define __io + +#endif /* _STARFIVE_VISIONFIVE2_H */