From patchwork Sun Dec 11 12:58:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1714595 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=gEmnCZS9; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NVPvt70jxz23yc for ; Sun, 11 Dec 2022 23:58:50 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0E192853AE; Sun, 11 Dec 2022 13:58:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="gEmnCZS9"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7B40185394; Sun, 11 Dec 2022 13:58:43 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.9 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, SPF_HELO_NONE,SPF_NONE autolearn=no autolearn_force=no version=3.4.2 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2A5BA853AE for ; Sun, 11 Dec 2022 13:58:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670763520; x=1702299520; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=doVVSIMq88kGKZUlO55f7fcwjGLaqRWHAievjBjlutg=; b=gEmnCZS9uRn8kuy34ONU+TcprpCPJi59VteSmMyrAC8cT5FWbwAFoFtD WP/zhvv4sCBjQUIolSQ6pD/8piMl5fbnx7XXpAvtVTBldbkv0UYa8iPsI 0K81TUPeaCXvLuKez4ATur39dm/41vAGwmkl9ioDDfzqRAMlgFUsaWbym BEQGfm3Ylmy0EseCQQ4UvlWzVjmuU8ShY+J4PHeo+JCG0g4fAPKVkSaG3 zFiFsqGGJLXYbjo64gJmnj9EJWwugOtz6EC55WosmpZG45EwtxoreYmCb 5S6KUvYNdZo+eJrd6wvxRQQ1wRvYfO+t3aXAGC4vqdNe+Pm0yi7h1CGbf w==; X-IronPort-AV: E=McAfee;i="6500,9779,10557"; a="298045750" X-IronPort-AV: E=Sophos;i="5.96,236,1665471600"; d="scan'208";a="298045750" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2022 04:58:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10557"; a="625599364" X-IronPort-AV: E=Sophos;i="5.96,236,1665471600"; d="scan'208";a="625599364" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga006.jf.intel.com with ESMTP; 11 Dec 2022 04:58:33 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 116472B0B; Sun, 11 Dec 2022 20:58:33 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id F2F0BE00218; Sun, 11 Dec 2022 20:58:32 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH] ddr: altera: n5x: Include DDR4 for the same hardcoding settings Date: Sun, 11 Dec 2022 20:58:31 +0800 Message-Id: <20221211125831.26258-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Below settings are required for DDR4 to get some DDR chips properly retention entry and exit. Register INIT0 = 0xF87F_80D0 = bits [31-30] = [11] Register PWRCTL = 0xF87F_8030 = bit [5] = 1 Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_n5x.c | 79 +++++----------------------------- 1 file changed, 10 insertions(+), 69 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index b4d52f7ac2..d2049520c8 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -341,7 +341,10 @@ enum region_size { enum reset_type { POR_RESET, WARM_RESET, - COLD_RESET + COLD_RESET, + NCONFIG, + JTAG_CONFIG, + RSU_RECONFIG }; enum ddr_type { @@ -394,16 +397,6 @@ enum message_mode { STREAMING_MESSAGE }; -/* Reset type */ -enum reset_type { - POR_RESET, - WARM_RESET, - COLD_RESET, - NCONFIG, - JTAG_CONFIG, - RSU_RECONFIG -}; - enum data_type { HEADER_ONLY, HEADER_DATA @@ -1013,14 +1006,13 @@ static int init_umctl2(phys_addr_t umctl2_handoff_base, /* Setting selfref_sw to 1, based on lpddr4 requirement */ setbits_le32(umctl2_base + DDR4_PWRCTL_OFFSET, DDR4_PWRCTL_SELFREF_SW); - /* Backup user settings, restore after DDR up running */ user_backup++; *user_backup = readl(umctl2_base + DDR4_INIT0_OFFSET) & DDR4_INIT0_SKIP_RAM_INIT; /* - * Setting INIT0.skip_dram_init to 0x3, based on lpddr4 + * Setting INIT0.skip_dram_init to 0x3, based on ddr4 / lpddr4 * requirement */ setbits_le32(umctl2_base + DDR4_INIT0_OFFSET, @@ -1614,8 +1606,6 @@ static bool is_cal_bak_data_valid(void) static int init_phy(struct ddr_handoff *ddr_handoff_info, bool *need_calibrate, bool is_ddr_hang_be4_rst) { - u32 handoff_table[ddr_handoff_info->phy_handoff_length]; - u32 i, value; u32 reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); int ret; @@ -2815,24 +2805,6 @@ static int ddr_post_config(struct ddr_handoff *handoff, bool *need_calibrate) return ret; } -static bool is_ddr_retention_enabled(u32 boot_scratch_cold0_reg) -{ - return boot_scratch_cold0_reg & - ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK; -} - -static bool is_ddr_bitstream_sha_matching(u32 boot_scratch_cold0_reg) -{ - return boot_scratch_cold0_reg & ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK; -} - -static enum reset_type get_reset_type(u32 boot_scratch_cold0_reg) -{ - return (boot_scratch_cold0_reg & - ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK) >> - ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT; -} - void reset_type_debug_print(u32 boot_scratch_cold0_reg) { switch (get_reset_type(boot_scratch_cold0_reg)) { @@ -2850,37 +2822,6 @@ void reset_type_debug_print(u32 boot_scratch_cold0_reg) } } -bool is_ddr_init(void) -{ - u32 reg = readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_BOOT_SCRATCH_COLD0); - - reset_type_debug_print(reg); - - if (get_reset_type(reg) == POR_RESET) { - debug("%s: DDR init is required\n", __func__); - return true; - } - - if (get_reset_type(reg) == WARM_RESET) { - debug("%s: DDR init is skipped\n", __func__); - return false; - } - - if (get_reset_type(reg) == COLD_RESET) { - if (is_ddr_retention_enabled(reg) && - is_ddr_bitstream_sha_matching(reg)) { - debug("%s: DDR retention bit is set\n", __func__); - debug("%s: Matching in DDR bistream\n", __func__); - debug("%s: DDR init is skipped\n", __func__); - return false; - } - } - - debug("%s: DDR init is required\n", __func__); - return true; -} - int sdram_mmr_init_full(struct udevice *dev) { u32 user_backup[2], user_backup_2nd[2]; @@ -2898,11 +2839,11 @@ int sdram_mmr_init_full(struct udevice *dev) printf("Checking SDRAM configuration in progress ...\n"); ret = populate_ddr_handoff(&ddr_handoff_info); - if (ret) { - debug("%s: Failed to populate DDR handoff\n", - __func__); - return ret; - } + if (ret) { + debug("%s: Failed to populate DDR handoff\n", + __func__); + return ret; + } /* Set the MPFE NoC mux to correct DDR controller type */ use_ddr4(ddr_handoff_info.cntlr_t);