diff mbox series

ddr: altera: n5x: Fixing debug log typo

Message ID 20221204143101.8031-1-jit.loon.lim@intel.com
State Needs Review / ACK, archived
Delegated to: Marek Vasut
Headers show
Series ddr: altera: n5x: Fixing debug log typo | expand

Commit Message

Jit Loon Lim Dec. 4, 2022, 2:31 p.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

Fixing debug log typo.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 drivers/ddr/altera/sdram_n5x.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
index 8a5f0a3df4..b4d52f7ac2 100644
--- a/drivers/ddr/altera/sdram_n5x.c
+++ b/drivers/ddr/altera/sdram_n5x.c
@@ -2345,7 +2345,7 @@  static void set_cal_res_to_rankctrl(u32 reg_addr, u16 update_value,
 
 	debug("max value divided by 2 is 0x%x\n", update_value);
 	debug("umclt2 register 0x%x value is 0%x before ", reg_addr, reg);
-	debug("update with train result\n");
+	debug("updating with train result\n");
 
 	value = (reg & mask) >> shift;
 
@@ -2365,8 +2365,8 @@  static void set_cal_res_to_rankctrl(u32 reg_addr, u16 update_value,
 	writel((reg & (~mask)) | value, (uintptr_t)reg_addr);
 
 	reg = readl((uintptr_t)reg_addr);
-	debug("umclt2 register 0x%x value is 0%x before ", reg_addr, reg);
-	debug("update with train result\n");
+	debug("umclt2 register 0x%x value is 0%x after ", reg_addr, reg);
+	debug("updating with train result\n");
 }
 
 /* helper function for updating train result to register */
@@ -2379,7 +2379,7 @@  static void set_cal_res_to_reg(u32 reg_addr, u16 update_value, u32 mask,
 
 	debug("max value divided by 2 is 0x%x\n", update_value);
 	debug("umclt2 register 0x%x value is 0%x before ", reg_addr, reg);
-	debug("update with train result\n");
+	debug("updating with train result\n");
 
 	value = (reg & mask) >> shift;
 
@@ -2389,8 +2389,8 @@  static void set_cal_res_to_reg(u32 reg_addr, u16 update_value, u32 mask,
 	writel((reg & (~mask)) | value, (uintptr_t)reg_addr);
 
 	reg = readl((uintptr_t)reg_addr);
-	debug("umclt2 register 0x%x value is 0%x before ", reg_addr, reg);
-	debug("update with train result\n");
+	debug("umclt2 register 0x%x value is 0%x after ", reg_addr, reg);
+	debug("updating with train result\n");
 }
 
 static u16 get_max_txdqsdlytg0_ux_p0(struct ddr_handoff *handoff, u32 reg,