From patchwork Wed Nov 23 14:17:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1708320 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=eeY8H+D+; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NHNWZ2RWlz23mR for ; Thu, 24 Nov 2022 01:18:02 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0929C852C7; Wed, 23 Nov 2022 15:17:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="eeY8H+D+"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D58FB852CC; Wed, 23 Nov 2022 15:17:54 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.9 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=no autolearn_force=no version=3.4.2 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0D9EA851F5 for ; Wed, 23 Nov 2022 15:17:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669213072; x=1700749072; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=QixRkOUbKp2ssCj9IWn+gqZszYNkAcjjJz5g6NR5gbA=; b=eeY8H+D+1jykULLlcglpYrjYbPuZ87m+/H9RItNdsq9/7mL7QXz+cDrA uZGDsJHj66DOspnyF4jjWbZPrQcCjfamNV9zzjSx4cGYFG+vF9LgFV+ZU SFjjeg2cH7D5dJxC+aVW2ZdlQ8n35LVU7g1HiCW73D/3xrkH5XdkUeZ9n pcSemG0FJrbp2eLfluRlAFM12aP8S7fkJP2Oljm6msksUhkLgNXmfQEA/ eW/5ZoUXPuQP9NvzQgWMvldKtrSxUtvQmTChoHi5b3CVLM3FPQ2VnfUw6 evDOJxShEPN7FXsIfz/evtBZroNqXFHNbilio36vpsEhVqQ9CB3MWxRvT w==; X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="301632787" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="301632787" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 06:17:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="710600223" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="710600223" Received: from pglmail07.png.intel.com ([10.221.193.207]) by fmsmga004.fm.intel.com with ESMTP; 23 Nov 2022 06:17:45 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id E940F482B; Wed, 23 Nov 2022 22:17:44 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id B7A93E0095B; Wed, 23 Nov 2022 22:17:44 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH] arm: socfpga: n5x: Update DDR init progress bit Date: Wed, 23 Nov 2022 22:17:41 +0800 Message-Id: <20221123141741.13101-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee The bit[30] of boot scratch cold 8 register is used as DDR init progress tracking by SDM when watchdog is triggered due to ddr init hang, so that SDM can run a clean reset to DDR subsystem. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/sdram_n5x.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 135bc8fd7d..d707bba862 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -428,6 +428,18 @@ enum data_process { LOADING }; +void ddr_init_inprogress(bool start) +{ + if (start) + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8, + ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK); + else + clrbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8, + ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK); +} + bool is_ddr_retention_enabled(u32 reg) { if (reg & ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK) @@ -2848,6 +2860,7 @@ int sdram_mmr_init_full(struct udevice *dev) if (!is_ddr_init_skipped(reg)) { printf("SDRAM init in progress ...\n"); + ddr_init_inprogress(true); /* * Polling reset complete, must be high to ensure DDR @@ -2994,6 +3007,10 @@ int sdram_mmr_init_full(struct udevice *dev) priv->info.size = gd->ram_size; sdram_size_check(&bd); + + /* Marking end of ddr init with passing basic memory test */ + ddr_init_inprogress(false); + sdram_set_firewall(&bd); ddr_offset = simple_strtoul(offset, &endptr, 16);