@@ -102,6 +102,19 @@ void populate_sysmgr_pinmux(void);
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK GENMASK(30, 28)
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28
+/*
+ * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD8
+ * Bit[31] reserved for FSBL to check DBE is triggered (set by SDM to "1") ?
+ *
+ * Bit[30] reserved for FSBL to update the DDR init progress
+ * 1 - means in progress, 0 - haven't started / DDR is up running.
+ *
+ * Bit[17:1] - Setting by Linux EDAC.
+ * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1)
+ */
+#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31)
+#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30)
+
#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)