@@ -97,7 +97,6 @@ config TARGET_SOCFPGA_N5X
select ARMV8_SET_SMPEN
select BINMAN if SPL_ATF
select CLK
- select FPGA_INTEL_SDM_MAILBOX
select NCORE_CACHE
select SPL_ALTERA_SDRAM
select SPL_CLK if SPL
@@ -64,11 +64,22 @@ obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
+obj-y += smmu_s10.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
+ifndef CONFIG_SPL_BUILD
+obj-y += rsu.o
+obj-y += rsu_ll_qspi.o
+obj-y += rsu_misc.o
+obj-y += rsu_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o
+endif
endif
ifdef CONFIG_SPL_BUILD