From patchwork Sat Nov 19 18:59:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hari Nagalla X-Patchwork-Id: 1706605 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=BET1sXm1; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NF37J1HQbz23mR for ; Sun, 20 Nov 2022 06:07:23 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 807FA8528E; Sat, 19 Nov 2022 20:07:19 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="BET1sXm1"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C5AD68528E; Sat, 19 Nov 2022 20:07:18 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1F57B852AE for ; Sat, 19 Nov 2022 20:00:31 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=hnagalla@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AJJ05Gv058078; Sat, 19 Nov 2022 13:00:05 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1668884405; bh=5Uy9vR7IR6SFhwCJ2DrO3jSytefhqHKsVrL8yTg+FFM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BET1sXm1C38Nyha4vC51zgpsyrCvLjivbVBbOcTONz4qtuiGjbsxPVjqG3rZiS9xK 6GQ2xtGZxdYPLNAuzQE71qeObBPaMkzwd7ALWXW2KU9yH7v4nzHDCSyiVmZKC5Datv CJYEqqP4GqPIzofdHdvW8Jrky8uTsazTQr0cl37c= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AJJ03aS031650 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 19 Nov 2022 13:00:04 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Sat, 19 Nov 2022 13:00:02 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Sat, 19 Nov 2022 13:00:02 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AJJ01sM122928; Sat, 19 Nov 2022 13:00:01 -0600 From: Hari Nagalla To: , , , , , , CC: , Subject: [PATCH 09/12] board: ti: j784s4: Add board support for J784S4 SoC Date: Sat, 19 Nov 2022 12:59:30 -0600 Message-ID: <20221119185933.16194-10-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221119185933.16194-1-hnagalla@ti.com> References: <20221119185933.16194-1-hnagalla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Add board support for J784S4 SoC. Signed-off-by: Hari Nagalla --- board/ti/j784s4/Kconfig | 61 ++++++++++++ board/ti/j784s4/MAINTAINERS | 7 ++ board/ti/j784s4/Makefile | 8 ++ board/ti/j784s4/evm.c | 180 ++++++++++++++++++++++++++++++++++++ 4 files changed, 256 insertions(+) create mode 100644 board/ti/j784s4/Kconfig create mode 100644 board/ti/j784s4/MAINTAINERS create mode 100644 board/ti/j784s4/Makefile create mode 100644 board/ti/j784s4/evm.c diff --git a/board/ti/j784s4/Kconfig b/board/ti/j784s4/Kconfig new file mode 100644 index 0000000000..9b6e3bb3c4 --- /dev/null +++ b/board/ti/j784s4/Kconfig @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +# Hari Nagalla + +choice + prompt "K3 J784S4 board" + optional + +config TARGET_J784S4_A72_EVM + bool "TI K3 based J784S4 EVM running on A72" + select ARM64 + select SOC_K3_J784S4 + select BOARD_LATE_INIT + select SYS_DISABLE_DCACHE_OPS + +config TARGET_J784S4_R5_EVM + bool "TI K3 based J784S4 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select SOC_K3_J784S4 + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + imply SYS_K3_SPL_ATF + +endchoice + +if TARGET_J784S4_A72_EVM + +config SYS_BOARD + default "j784s4" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "j784s4_evm" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_J784S4_R5_EVM + +config SYS_BOARD + default "j784s4" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "j784s4_evm" + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +source "board/ti/common/Kconfig" + +endif diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS new file mode 100644 index 0000000000..7b45e409c6 --- /dev/null +++ b/board/ti/j784s4/MAINTAINERS @@ -0,0 +1,7 @@ +J784S4 BOARD +M: Hari Nagalla +S: Maintained +F: board/ti/j784s4 +F: include/configs/j784s4_evm.h +F: configs/j784s4_evm_r5_defconfig +F: configs/j784s4_evm_a72_defconfig diff --git a/board/ti/j784s4/Makefile b/board/ti/j784s4/Makefile new file mode 100644 index 0000000000..fc98b24a2d --- /dev/null +++ b/board/ti/j784s4/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +# Hari Nagalla +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evm.o diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c new file mode 100644 index 0000000000..155abe53ca --- /dev/null +++ b/board/ti/j784s4/evm.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board specific initialization for J784S4 EVM + * + * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/ + * Hari Nagalla + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/board_detect.h" + +#define board_is_j784s4_evm() board_ti_k3_is("J784S4-EVM") + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ +#ifdef CONFIG_PHYS_64BIT + gd->ram_size = 0x100000000; +#else + gd->ram_size = 0x80000000; +#endif + + return 0; +} + +phys_size_t board_get_usable_ram_top(phys_size_t total_size) +{ +#ifdef CONFIG_PHYS_64BIT + /* Limit RAM used by U-Boot to the DDR low region */ + if (gd->ram_top > 0x100000000) + return 0x100000000; +#endif + + return gd->ram_top; +} + +int dram_init_banksize(void) +{ + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x7fffffff; + gd->ram_size = 0x80000000; + +#ifdef CONFIG_PHYS_64BIT + /* Bank 1 declares the memory available in the DDR high region */ + gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].size = 0x77fffffff; + gd->ram_size = 0x800000000; +#endif + + return 0; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (!strcmp(name, "J784S4X-EVM")) + return 0; + + return -1; +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int ret; + + ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000"); + if (ret < 0) + ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", + "sram@70000000"); + if (ret) + printf("%s: fixing up msmc ram failed %d\n", __func__, ret); + + return ret; +} +#endif + +#ifdef CONFIG_TI_I2C_BOARD_DETECT +int do_board_detect(void) +{ + int ret; + + ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS); + if (ret) + pr_err("Reading on-board EEPROM at 0x%02x failed %d\n", + CONFIG_EEPROM_CHIP_ADDRESS, ret); + + return ret; +} + +int checkboard(void) +{ + struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA; + + if (do_board_detect()) + /* EEPROM not populated */ + printf("Board: %s rev %s\n", "J784S4-EVM", "E1"); + else + printf("Board: %s rev %s\n", ep->name, ep->version); + + return 0; +} + +static void setup_board_eeprom_env(void) +{ + char *name = "j784s4"; + + if (do_board_detect()) + goto invalid_eeprom; + + if (board_is_j784s4_evm()) + name = "j784s4"; + else + printf("Unidentified board claims %s in eeprom header\n", + board_ti_get_name()); + +invalid_eeprom: + set_board_info_env_am6(name); +} + +static void setup_serial(void) +{ + struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA; + unsigned long board_serial; + char *endp; + char serial_string[17] = { 0 }; + + if (env_get("serial#")) + return; + + board_serial = simple_strtoul(ep->serial, &endp, 16); + if (*endp != '\0') { + pr_err("Error: Can't set serial# to %s\n", ep->serial); + return; + } + + snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial); + env_set("serial#", serial_string); +} +#endif + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) { + setup_board_eeprom_env(); + setup_serial(); + } + + return 0; +} + +void spl_board_init(void) +{ +}