diff mbox series

[1/5] arm: socfpga: Add F2SDRAM_MANAGER base address

Message ID 20221113145706.5002-1-jit.loon.lim@intel.com
State Needs Review / ACK, archived
Delegated to: Marek Vasut
Headers show
Series [1/5] arm: socfpga: Add F2SDRAM_MANAGER base address | expand

Commit Message

Jit Loon Lim Nov. 13, 2022, 2:57 p.m. UTC 
From: Ley Foon Tan <ley.foon.tan@intel.com>

HSD #1508586908-1: Add F2SDRAM Manager base address.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 .../include/mach/reset_manager_soc64.h        | 26 ++++++++++++++++---
 1 file changed, 22 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index c8bb727aa2..ca5739c30c 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -1,6 +1,6 @@ 
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- *  Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *  Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
  */
 
 #ifndef _RESET_MANAGER_SOC64_H_
@@ -12,15 +12,33 @@  void print_reset_info(void);
 void socfpga_bridges_reset(int enable);
 
 #define RSTMGR_SOC64_STATUS	0x00
+#define RSTMGR_SOC64_HDSKEN	0x10
+#define RSTMGR_SOC64_HDSKREQ	0x14
+#define RSTMGR_SOC64_HDSKACK	0x18
 #define RSTMGR_SOC64_MPUMODRST	0x20
 #define RSTMGR_SOC64_PER0MODRST	0x24
 #define RSTMGR_SOC64_PER1MODRST	0x28
 #define RSTMGR_SOC64_BRGMODRST	0x2c
 
-#define RSTMGR_MPUMODRST_CORE0		0
+#define RSTMGR_MPUMODRST_CORE0	0
 #define RSTMGR_PER0MODRST_OCP_MASK	0x0020bf00
-#define RSTMGR_BRGMODRST_DDRSCH_MASK	0X00000040
-#define RSTMGR_BRGMODRST_FPGA2SOC_MASK	0x00000004
+#define RSTMGR_BRGMODRST_SOC2FPGA_MASK	BIT(0)
+#define RSTMGR_BRGMODRST_LWSOC2FPGA_MASK	BIT(1)
+#define RSTMGR_BRGMODRST_FPGA2SOC_MASK	BIT(2)
+#define RSTMGR_BRGMODRST_F2SDRAM0_MASK	BIT(3)
+#define RSTMGR_BRGMODRST_F2SDRAM1_MASK	BIT(4)
+#define RSTMGR_BRGMODRST_F2SDRAM2_MASK	BIT(5)
+#define RSTMGR_BRGMODRST_DDRSCH_MASK	BIT(6)
+
+#define BRGMODRST_SOC2FPGA_BRIDGES	(RSTMGR_BRGMODRST_SOC2FPGA_MASK | \
+					 RSTMGR_BRGMODRST_LWSOC2FPGA_MASK)
+#define BRGMODRST_FPGA2SOC_BRIDGES	(RSTMGR_BRGMODRST_FPGA2SOC_MASK | \
+					 RSTMGR_BRGMODRST_F2SDRAM0_MASK | \
+					 RSTMGR_BRGMODRST_F2SDRAM1_MASK | \
+					 RSTMGR_BRGMODRST_F2SDRAM2_MASK)
+
+#define RSTMGR_HDSKEN_FPGAHSEN		BIT(2)
+#define RSTMGR_HDSKREQ_FPGAHSREQ	BIT(2)
 
 /* SDM, Watchdogs and MPU warm reset mask */
 #define RSTMGR_STAT_SDMWARMRST		BIT(1)