Message ID | 20221004110750.2959466-5-martyn.welch@collabora.com |
---|---|
State | Changes Requested |
Delegated to: | Stefano Babic |
Headers | show |
Series | [v4,1/5] imx8m: USDHC3 base address definition for i.MX8MP | expand |
On 04.10.22 13:07, Martyn Welch wrote: > Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction > with the MSC SM2-MB-EP1 Mini-ITX Carrier Board. I see at least some issues: - MAINTAINERS file is missing - a lot of symbols are set in include/configs/msc_sm2s_imx8mp.h instead of moving to Kbuild. Running first CI, the following are reported: Unmigrated symbols found in include/configs/msc_sm2s_imx8mp.h: CONFIG_ETHPRIME CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_STACK CONFIG_SYS_BARGSIZE CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR CONFIG_SYS_SPL_MALLOC_SIZE Unmigrated symbols found in include/configs/imx7ulp_spl.h: CONFIG_SPL_FS_LOAD_PAYLOAD_NAME CONFIG_SPL_STACK CONFIG_SYS_MMCSD_FS_BOOT_PARTITION CONFIG_SYS_SPL_MALLOC_SIZE Best regards, Stefano > > Signed-off-by: Martyn Welch <martyn.welch@collabora.com> > --- > > Changes in v2: > - Renamed FDT to closer match kernel > - Sync with kernel FDT > - Update for changes made in U-Boot > > Changes in v3: > - Use imx8mp-u-boot.dtsi > - Switch to use of DM PMIC support in SPL > > Changes in v4: > - Rebased to latest imx master branch > > arch/arm/dts/Makefile | 1 + > arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi | 65 + > arch/arm/dts/imx8mp-msc-sm2s.dts | 820 ++++++++ > arch/arm/mach-imx/imx8m/Kconfig | 8 + > board/msc/sm2s_imx8mp/Kconfig | 15 + > board/msc/sm2s_imx8mp/Makefile | 12 + > board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg | 8 + > board/msc/sm2s_imx8mp/lpddr4_timing.c | 1842 +++++++++++++++++ > board/msc/sm2s_imx8mp/sm2s_imx8mp.c | 60 + > board/msc/sm2s_imx8mp/spl.c | 273 +++ > configs/msc_sm2s_imx8mp_defconfig | 91 + > include/configs/msc_sm2s_imx8mp.h | 96 + > 12 files changed, 3291 insertions(+) > create mode 100644 arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi > create mode 100644 arch/arm/dts/imx8mp-msc-sm2s.dts > create mode 100644 board/msc/sm2s_imx8mp/Kconfig > create mode 100644 board/msc/sm2s_imx8mp/Makefile > create mode 100644 board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg > create mode 100644 board/msc/sm2s_imx8mp/lpddr4_timing.c > create mode 100644 board/msc/sm2s_imx8mp/sm2s_imx8mp.c > create mode 100644 board/msc/sm2s_imx8mp/spl.c > create mode 100644 configs/msc_sm2s_imx8mp_defconfig > create mode 100644 include/configs/msc_sm2s_imx8mp.h > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 965895bc2a..a5de6e1b5e 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -970,6 +970,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ > imx8mq-phanbell.dtb \ > imx8mp-dhcom-pdk2.dtb \ > imx8mp-evk.dtb \ > + imx8mp-msc-sm2s.dtb \ > imx8mp-phyboard-pollux-rdk.dtb \ > imx8mp-venice.dtb \ > imx8mp-venice-gw74xx.dtb \ > diff --git a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi > new file mode 100644 > index 0000000000..cf591adf5a > --- /dev/null > +++ b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi > @@ -0,0 +1,65 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2019 NXP > + */ > + > +#include "imx8mp-u-boot.dtsi" > + > +/ { > + model = "MSC SM2S-IMX8MPLUS"; > + compatible = "avnet,sm2s-imx8mp", "fsl,imx8mp"; > + > + wdt-reboot { > + compatible = "wdt-reboot"; > + wdt = <&wdog1>; > + u-boot,dm-spl; > + }; > +}; > + > +®_usdhc2_vmmc { > + u-boot,dm-spl; > +}; > + > +&gpio1 { > + u-boot,dm-spl; > +}; > + > +&gpio2 { > + u-boot,dm-spl; > +}; > + > +&gpio3 { > + u-boot,dm-spl; > +}; > + > +&i2c1 { > + u-boot,dm-spl; > +}; > + > +&i2c2 { > + u-boot,dm-spl; > +}; > + > +&i2c3 { > + u-boot,dm-spl; > +}; > + > +&i2c4 { > + u-boot,dm-spl; > +}; > + > +&i2c5 { > + u-boot,dm-spl; > +}; > + > +&i2c6 { > + u-boot,dm-spl; > +}; > + > +&pinctrl_i2c6 { > + u-boot,dm-spl; > +}; > + > +&pmic { > + u-boot,dm-spl; > +}; > diff --git a/arch/arm/dts/imx8mp-msc-sm2s.dts b/arch/arm/dts/imx8mp-msc-sm2s.dts > new file mode 100644 > index 0000000000..5dbec71747 > --- /dev/null > +++ b/arch/arm/dts/imx8mp-msc-sm2s.dts > @@ -0,0 +1,820 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2022 Avnet Embedded GmbH > + */ > + > +/dts-v1/; > + > +#include "imx8mp.dtsi" > +#include <dt-bindings/net/ti-dp83867.h> > + > +/ { > + aliases { > + rtc0 = &sys_rtc; > + rtc1 = &snvs_rtc; > + }; > + > + chosen { > + stdout-path = &uart2; > + }; > + > + reg_usb0_host_vbus: regulator-usb0-vbus { > + compatible = "regulator-fixed"; > + regulator-name = "usb0_host_vbus"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usb0_vbus>; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reg_usb1_host_vbus: regulator-usb1-vbus { > + compatible = "regulator-fixed"; > + regulator-name = "usb1_host_vbus"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usb1_vbus>; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reg_usdhc2_vmmc: regulator-usdhc2 { > + compatible = "regulator-fixed"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; > + regulator-name = "VSD_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + startup-delay-us = <100>; > + off-on-delay-us = <12000>; > + }; > + > + reg_flexcan1_xceiver: regulator-flexcan1 { > + compatible = "regulator-fixed"; > + regulator-name = "flexcan1-xceiver"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > + > + reg_flexcan2_xceiver: regulator-flexcan2 { > + compatible = "regulator-fixed"; > + regulator-name = "flexcan2-xceiver"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > + > + lcd0_backlight: backlight-0 { > + compatible = "pwm-backlight"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lcd0_backlight>; > + pwms = <&pwm1 0 100000 0>; > + brightness-levels = <0 255>; > + num-interpolated-steps = <255>; > + default-brightness-level = <255>; > + enable-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; > + status = "disabled"; > + }; > + > + lcd1_backlight: backlight-1 { > + compatible = "pwm-backlight"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lcd1_backlight>; > + pwms = <&pwm2 0 100000 0>; > + brightness-levels = <0 255>; > + num-interpolated-steps = <255>; > + default-brightness-level = <255>; > + enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; > + status = "disabled"; > + }; > + > + leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_leds>; > + status = "okay"; > + > + led-sw { > + label = "sw-led"; > + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; > + default-state = "off"; > + linux,default-trigger = "heartbeat"; > + }; > + }; > + > + extcon_usb0: extcon-usb0 { > + compatible = "linux,extcon-usb-gpio"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usb0_extcon>; > + id-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; > + }; > +}; > + > +&A53_0 { > + cpu-supply = <&vcc_arm>; > +}; > + > +&A53_1 { > + cpu-supply = <&vcc_arm>; > +}; > + > +&A53_2 { > + cpu-supply = <&vcc_arm>; > +}; > + > +&A53_3 { > + cpu-supply = <&vcc_arm>; > +}; > + > +&ecspi1 { > + #address-cells = <1>; > + #size-cells = <0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi1>; > + cs-gpios = <0>, <&gpio2 8 GPIO_ACTIVE_LOW>; > +}; > + > +&ecspi2 { > + #address-cells = <1>; > + #size-cells = <0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi2>; > + cs-gpios = <0>, <&gpio2 9 GPIO_ACTIVE_LOW>; > +}; > + > +&eqos { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_eqos>; > + phy-mode = "rgmii-id"; > + phy-handle = <ðphy0>; > + status = "okay"; > + > + mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy0: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + eee-broken-1000t; > + reset-gpios = <&tca6424 16 GPIO_ACTIVE_LOW>; > + reset-assert-us = <1000>; > + reset-deassert-us = <1000>; > + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; > + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; > + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; > + }; > + }; > +}; > + > +&fec { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec>; > + phy-mode = "rgmii-id"; > + phy-handle = <ðphy1>; > + fsl,magic-packet; > + status = "okay"; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy1: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + eee-broken-1000t; > + reset-gpios = <&tca6424 17 GPIO_ACTIVE_LOW>; > + reset-assert-us = <1000>; > + reset-deassert-us = <1000>; > + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; > + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; > + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; > + }; > + }; > +}; > + > +&i2c1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c1>; > + clock-frequency = <400000>; > + status = "okay"; > + > + id_eeprom: eeprom@50 { > + compatible = "atmel,24c64"; > + reg = <0x50>; > + pagesize = <32>; > + }; > +}; > + > +&i2c2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c2>; > + clock-frequency = <400000>; > + status = "disabled"; > +}; > + > +&i2c3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c3>; > + clock-frequency = <400000>; > + status = "disabled"; > +}; > + > +&i2c4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c4>; > + clock-frequency = <400000>; > + status = "disabled"; > +}; > + > +&i2c5 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c5>; > + clock-frequency = <400000>; > + status = "disabled"; > +}; > + > +&i2c6 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c6>; > + clock-frequency = <400000>; > + status = "okay"; > + > + tca6424: gpio@22 { > + compatible = "ti,tca6424"; > + reg = <0x22>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_tca6424>; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-line-names = "BOOT_SEL0#", "BOOT_SEL1#", "BOOT_SEL2#", > + "gbe0_int", "gbe1_int", "pmic_int", "rtc_int", "lvds_int", > + "PCIE_WAKE#", "cam2_rst", "cam2_pwr", "SLEEP#", > + "wifi_pd", "tpm_int", "wifi_int", "PCIE_A_RST#", > + "gbe0_rst", "gbe1_rst", "LID#", "BATLOW#", "CHARGING#", > + "CHARGER_PRSNT#"; > + interrupt-parent = <&gpio1>; > + interrupts = <9 IRQ_TYPE_EDGE_RISING>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + dsi_lvds_bridge: bridge@2d { > + compatible = "ti,sn65dsi83"; > + reg = <0x2d>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lvds_bridge>; > + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; > + status = "disabled"; > + }; > + > + pmic: pmic@30 { > + compatible = "ricoh,rn5t567"; > + reg = <0x30>; > + interrupt-parent = <&tca6424>; > + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; > + > + regulators { > + DCDC1 { > + regulator-name = "VCC_SOC"; > + regulator-always-on; > + regulator-min-microvolt = <950000>; > + regulator-max-microvolt = <950000>; > + }; > + > + DCDC2 { > + regulator-name = "VCC_DRAM"; > + regulator-always-on; > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1100000>; > + }; > + > + vcc_arm: DCDC3 { > + regulator-name = "VCC_ARM"; > + regulator-always-on; > + regulator-min-microvolt = <950000>; > + regulator-max-microvolt = <950000>; > + }; > + > + DCDC4 { > + regulator-name = "VCC_1V8"; > + regulator-always-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > + > + LDO1 { > + regulator-name = "VCC_LDO1_2V5"; > + regulator-always-on; > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + }; > + > + LDO2 { > + regulator-name = "VCC_LDO2_1V8"; > + regulator-always-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > + > + LDO3 { > + regulator-name = "VCC_ETH_2V5"; > + regulator-always-on; > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + }; > + > + LDO4 { > + regulator-name = "VCC_DDR4_2V5"; > + regulator-always-on; > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + }; > + > + LDO5 { > + regulator-name = "VCC_LDO5_1V8"; > + regulator-always-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > + > + LDORTC1 { > + regulator-name = "VCC_SNVS_1V8"; > + regulator-always-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > + > + LDORTC2 { > + regulator-name = "VCC_SNVS_3V3"; > + regulator-always-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > + }; > + }; > + > + sys_rtc: rtc@32 { > + compatible = "ricoh,r2221tl"; > + reg = <0x32>; > + interrupt-parent = <&tca6424>; > + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; > + }; > + > + tmp_sensor: temperature-sensor@71 { > + compatible = "ti,tmp103"; > + reg = <0x71>; > + }; > +}; > + > +&flexcan1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan1>; > + xceiver-supply = <®_flexcan1_xceiver>; > + status = "disabled"; > +}; > + > +&flexcan2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan2>; > + xceiver-supply = <®_flexcan2_xceiver>; > + status = "disabled"; > +}; > + > +&flexspi { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexspi0>; > + status = "okay"; > + > + qspi_flash: flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <1>; > + spi-max-frequency = <80000000>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > + }; > +}; > + > +&pwm1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm1>; > + status = "disabled"; > +}; > + > +&pwm2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm2>; > + status = "disabled"; > +}; > + > +&pwm3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm3>; > + status = "disabled"; > +}; > + > +&pwm4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm4>; > + status = "disabled"; > +}; > + > +&snvs_pwrkey { > + status = "okay"; > +}; > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + status = "okay"; > +}; > + > +&uart2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart2>; > + uart-has-rtscts; > + status = "okay"; > +}; > + > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > + uart-has-rtscts; > + status = "okay"; > +}; > + > +&uart4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart4>; > + status = "disabled"; > +}; > + > +&usb3_phy0 { > + vbus-supply = <®_usb0_host_vbus>; > + status = "okay"; > +}; > + > +&usb3_phy1 { > + vbus-supply = <®_usb1_host_vbus>; > + status = "okay"; > +}; > + > +&usb3_0 { > + status = "okay"; > +}; > + > +&usb3_1 { > + status = "okay"; > +}; > + > +&usb_dwc3_0 { > + dr_mode = "otg"; > + hnp-disable; > + srp-disable; > + adp-disable; > + extcon = <&extcon_usb0>; > + status = "okay"; > +}; > + > +&usb_dwc3_1 { > + dr_mode = "host"; > + status = "okay"; > +}; > + > +&usdhc2 { > + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; > + assigned-clock-rates = <400000000>; > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; > + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; > + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; > + bus-width = <4>; > + vmmc-supply = <®_usdhc2_vmmc>; > + status = "okay"; > +}; > + > +&usdhc3 { > + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; > + assigned-clock-rates = <400000000>; > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc3>; > + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; > + bus-width = <8>; > + non-removable; > + status = "okay"; > +}; > + > +&wdog1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_wdog>; > + fsl,ext-reset-output; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_ecspi1: ecspi1grp { > + fsl,pins = > + <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82>, > + <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82>, > + <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82>, > + <MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x40000>, > + <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x40000>; > + }; > + > + pinctrl_ecspi2: ecspi2grp { > + fsl,pins = > + <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82>, > + <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82>, > + <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82>, > + <MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x40000>, > + <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x40000>; > + }; > + > + pinctrl_eqos: eqosgrp { > + fsl,pins = > + <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>, > + <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>, > + <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>, > + <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>, > + <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>, > + <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>, > + <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>, > + <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>, > + <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>, > + <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>, > + <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>, > + <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>, > + <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>, > + <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>; > + }; > + > + pinctrl_fec: fecgrp { > + fsl,pins = > + <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, > + <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, > + <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, > + <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, > + <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, > + <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, > + <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, > + <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, > + <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, > + <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, > + <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, > + <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, > + <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, > + <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>; > + }; > + > + pinctrl_flexcan1: flexcan1grp { > + fsl,pins = > + <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154>, > + <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154>; > + }; > + > + pinctrl_flexcan2: flexcan2grp { > + fsl,pins = > + <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154>, > + <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154>; > + }; > + > + pinctrl_flexspi0: flexspi0grp { > + fsl,pins = > + <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, > + <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, > + <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, > + <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, > + <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, > + <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, > + <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x19>; > + }; > + > + pinctrl_i2c1: i2c1grp { > + fsl,pins = > + <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3>, > + <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3>; > + }; > + > + pinctrl_i2c2: i2c2grp { > + fsl,pins = > + <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3>, > + <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3>; > + }; > + > + pinctrl_i2c3: i2c3grp { > + fsl,pins = > + <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3>, > + <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3>; > + }; > + > + pinctrl_i2c4: i2c4grp { > + fsl,pins = > + <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3>, > + <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3>; > + }; > + > + pinctrl_i2c5: i2c5grp { > + fsl,pins = > + <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3>, > + <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3>; > + }; > + > + pinctrl_i2c6: i2c6grp { > + fsl,pins = > + <MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3>, > + <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3>; > + }; > + > + pinctrl_lcd0_backlight: lcd0-backlightgrp { > + fsl,pins = > + <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41>; > + }; > + > + pinctrl_lcd1_backlight: lcd1-backlightgrp { > + fsl,pins = > + <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x41>; > + }; > + > + pinctrl_leds: ledsgrp { > + fsl,pins = > + <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19>; > + }; > + > + pinctrl_lvds_bridge: lvds-bridgegrp { > + fsl,pins = > + <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x41>; > + }; > + > + pinctrl_pwm1: pwm1grp { > + fsl,pins = > + <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116>; > + }; > + > + pinctrl_pwm2: pwm2grp { > + fsl,pins = > + <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116>; > + }; > + > + pinctrl_pwm3: pwm3grp { > + fsl,pins = > + <MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x116>; > + }; > + > + pinctrl_pwm4: pwm4grp { > + fsl,pins = > + <MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116>; > + }; > + > + pinctrl_tca6424: tca6424grp { > + fsl,pins = > + <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x41>; > + }; > + > + pinctrl_uart1: uart1grp { > + fsl,pins = > + <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49>, > + <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49>; > + }; > + > + pinctrl_uart2: uart2grp { > + fsl,pins = > + <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x1c4>, > + <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x1c4>, > + <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49>, > + <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49>; > + }; > + > + pinctrl_uart3: uart3grp { > + fsl,pins = > + <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>, > + <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x1c4>, > + <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49>, > + <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49>; > + }; > + > + pinctrl_uart4: uart4grp { > + fsl,pins = > + <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49>, > + <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49>; > + }; > + > + pinctrl_usb0_extcon: usb0-extcongrp { > + fsl,pins = > + <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x19>; > + }; > + > + pinctrl_usb0_vbus: usb0-vbusgrp { > + fsl,pins = > + <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19>; > + }; > + > + pinctrl_usb1_vbus: usb1-vbusgrp { > + fsl,pins = > + <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19>; > + }; > + > + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { > + fsl,pins = > + <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>, > + <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4>; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = > + <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, > + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, > + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, > + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, > + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, > + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>, > + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>; > + }; > + > + pinctrl_usdhc2_vmmc: usdhc2-vmmcgrp { > + fsl,pins = > + <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41>; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > + fsl,pins = > + <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, > + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, > + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, > + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, > + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, > + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, > + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > + fsl,pins = > + <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, > + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, > + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, > + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, > + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, > + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>, > + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>; > + }; > + > + pinctrl_usdhc3: usdhc3grp { > + fsl,pins = > + <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, > + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>, > + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, > + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, > + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, > + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, > + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, > + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, > + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, > + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, > + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>; > + }; > + > + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { > + fsl,pins = > + <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, > + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, > + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, > + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, > + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, > + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, > + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, > + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, > + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, > + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, > + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>; > + }; > + > + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { > + fsl,pins = > + <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, > + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>, > + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6>, > + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6>, > + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6>, > + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6>, > + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6>, > + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6>, > + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6>, > + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6>, > + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>; > + }; > + > + pinctrl_wdog: wdoggrp { > + fsl,pins = > + <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; > + }; > +}; > diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig > index 3470160990..ee62b958a8 100644 > --- a/arch/arm/mach-imx/imx8m/Kconfig > +++ b/arch/arm/mach-imx/imx8m/Kconfig > @@ -270,6 +270,13 @@ config TARGET_IMX8MP_RSB3720A1_6G > select SUPPORT_SPL > select IMX8M_LPDDR4 > > +config TARGET_MSC_SM2S_IMX8MP > + bool "MSC SMARC2 i.MX8MPLUS" > + select BINMAN > + select IMX8MP > + select SUPPORT_SPL > + select IMX8M_LPDDR4 > + > config TARGET_LIBREM5 > bool "Purism Librem5 Phone" > select BINMAN > @@ -296,6 +303,7 @@ source "board/google/imx8mq_phanbell/Kconfig" > source "board/kontron/pitx_imx8m/Kconfig" > source "board/kontron/sl-mx8mm/Kconfig" > source "board/menlo/mx8menlo/Kconfig" > +source "board/msc/sm2s_imx8mp/Kconfig" > source "board/phytec/phycore_imx8mm/Kconfig" > source "board/phytec/phycore_imx8mp/Kconfig" > source "board/purism/librem5/Kconfig" > diff --git a/board/msc/sm2s_imx8mp/Kconfig b/board/msc/sm2s_imx8mp/Kconfig > new file mode 100644 > index 0000000000..f71a5b2bcd > --- /dev/null > +++ b/board/msc/sm2s_imx8mp/Kconfig > @@ -0,0 +1,15 @@ > +if TARGET_MSC_SM2S_IMX8MP > + > +config SYS_BOARD > + default "sm2s_imx8mp" > + > +config SYS_VENDOR > + default "msc" > + > +config SYS_CONFIG_NAME > + default "msc_sm2s_imx8mp" > + > +config IMX_CONFIG > + default "board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg" > + > +endif > diff --git a/board/msc/sm2s_imx8mp/Makefile b/board/msc/sm2s_imx8mp/Makefile > new file mode 100644 > index 0000000000..f60dd7260c > --- /dev/null > +++ b/board/msc/sm2s_imx8mp/Makefile > @@ -0,0 +1,12 @@ > +# > +# Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH > +# > +# SPDX-License-Identifier: GPL-2.0 > +# > + > +ifdef CONFIG_SPL_BUILD > +obj-y += spl.o lpddr4_timing.o > +else > +obj-y += sm2s_imx8mp.o > +endif > + > diff --git a/board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg b/board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg > new file mode 100644 > index 0000000000..8aadedb102 > --- /dev/null > +++ b/board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg > @@ -0,0 +1,8 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright 2021 NXP > + */ > + > +ROM_VERSION v2 > +BOOT_FROM sd > +LOADER u-boot-spl-ddr.bin 0x920000 > diff --git a/board/msc/sm2s_imx8mp/lpddr4_timing.c b/board/msc/sm2s_imx8mp/lpddr4_timing.c > new file mode 100644 > index 0000000000..e0d659af91 > --- /dev/null > +++ b/board/msc/sm2s_imx8mp/lpddr4_timing.c > @@ -0,0 +1,1842 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2019 NXP > + */ > + > +#include <linux/kernel.h> > +#include <asm/arch/ddr.h> > + > +static struct dram_cfg_param ddr_ddrc_cfg[] = { > + /** Initialize DDRC registers **/ > + { 0x3d400304, 0x1 }, > + { 0x3d400030, 0x1 }, > + { 0x3d400000, 0xa1080020 }, > + { 0x3d400020, 0x1223 }, > + { 0x3d400024, 0x16e3600 }, > + { 0x3d400064, 0x5b00d2 }, > + { 0x3d400070, 0x61027f10 }, > + { 0x3d400074, 0x7b0 }, > + { 0x3d4000d0, 0xc00305ba }, > + { 0x3d4000d4, 0x940000 }, > + { 0x3d4000dc, 0xd4002d }, > + { 0x3d4000e0, 0x330000 }, > + { 0x3d4000e8, 0x660048 }, > + { 0x3d4000ec, 0x160048 }, > + { 0x3d400100, 0x191e1920 }, > + { 0x3d400104, 0x60630 }, > + { 0x3d40010c, 0xb0b000 }, > + { 0x3d400110, 0xe04080e }, > + { 0x3d400114, 0x2040c0c }, > + { 0x3d400118, 0x1010007 }, > + { 0x3d40011c, 0x401 }, > + { 0x3d400130, 0x20600 }, > + { 0x3d400134, 0xc100002 }, > + { 0x3d400138, 0xd8 }, > + { 0x3d400144, 0x96004b }, > + { 0x3d400180, 0x2ee0017 }, > + { 0x3d400184, 0x2605b8e }, > + { 0x3d400188, 0x0 }, > + { 0x3d400190, 0x497820a }, > + { 0x3d400194, 0x80303 }, > + { 0x3d4001b4, 0x170a }, > + { 0x3d4001a0, 0xe0400018 }, > + { 0x3d4001a4, 0xdf00e4 }, > + { 0x3d4001a8, 0x80000000 }, > + { 0x3d4001b0, 0x11 }, > + { 0x3d4001c0, 0x1 }, > + { 0x3d4001c4, 0x1 }, > + { 0x3d4000f4, 0xc99 }, > + { 0x3d400108, 0x70e1617 }, > + { 0x3d400200, 0x1f }, > + { 0x3d40020c, 0x0 }, > + { 0x3d400210, 0x1f1f }, > + { 0x3d400204, 0x80808 }, > + { 0x3d400214, 0x7070707 }, > + { 0x3d400218, 0x7070707 }, > + { 0x3d40021c, 0xf0f }, > + { 0x3d400250, 0x1705 }, > + { 0x3d400254, 0x2c }, > + { 0x3d40025c, 0x4000030 }, > + { 0x3d400264, 0x900093e7 }, > + { 0x3d40026c, 0x2005574 }, > + { 0x3d400400, 0x111 }, > + { 0x3d400404, 0x72ff }, > + { 0x3d400408, 0x72ff }, > + { 0x3d400494, 0x2100e07 }, > + { 0x3d400498, 0x620096 }, > + { 0x3d40049c, 0x1100e07 }, > + { 0x3d4004a0, 0xc8012c }, > + { 0x3d402020, 0x1021 }, > + { 0x3d402024, 0x30d400 }, > + { 0x3d402050, 0x20d000 }, > + { 0x3d402064, 0xc001c }, > + { 0x3d4020dc, 0x840000 }, > + { 0x3d4020e0, 0x330000 }, > + { 0x3d4020e8, 0x660048 }, > + { 0x3d4020ec, 0x160048 }, > + { 0x3d402100, 0xa040305 }, > + { 0x3d402104, 0x30407 }, > + { 0x3d402108, 0x203060b }, > + { 0x3d40210c, 0x505000 }, > + { 0x3d402110, 0x2040202 }, > + { 0x3d402114, 0x2030202 }, > + { 0x3d402118, 0x1010004 }, > + { 0x3d40211c, 0x301 }, > + { 0x3d402130, 0x20300 }, > + { 0x3d402134, 0xa100002 }, > + { 0x3d402138, 0x1d }, > + { 0x3d402144, 0x14000a }, > + { 0x3d402180, 0x640004 }, > + { 0x3d402190, 0x3818200 }, > + { 0x3d402194, 0x80303 }, > + { 0x3d4021b4, 0x100 }, > + { 0x3d4020f4, 0xc99 }, > + { 0x3d403020, 0x1021 }, > + { 0x3d403024, 0xc3500 }, > + { 0x3d403050, 0x20d000 }, > + { 0x3d403064, 0x30007 }, > + { 0x3d4030dc, 0x840000 }, > + { 0x3d4030e0, 0x330000 }, > + { 0x3d4030e8, 0x660048 }, > + { 0x3d4030ec, 0x160048 }, > + { 0x3d403100, 0xa010102 }, > + { 0x3d403104, 0x30404 }, > + { 0x3d403108, 0x203060b }, > + { 0x3d40310c, 0x505000 }, > + { 0x3d403110, 0x2040202 }, > + { 0x3d403114, 0x2030202 }, > + { 0x3d403118, 0x1010004 }, > + { 0x3d40311c, 0x301 }, > + { 0x3d403130, 0x20300 }, > + { 0x3d403134, 0xa100002 }, > + { 0x3d403138, 0x8 }, > + { 0x3d403144, 0x50003 }, > + { 0x3d403180, 0x190004 }, > + { 0x3d403190, 0x3818200 }, > + { 0x3d403194, 0x80303 }, > + { 0x3d4031b4, 0x100 }, > + { 0x3d4030f4, 0xc99 }, > + { 0x3d400028, 0x0 }, > +}; > + > +/* PHY Initialize Configuration */ > +static struct dram_cfg_param ddr_ddrphy_cfg[] = { > + { 0x100a0, 0x0 }, > + { 0x100a1, 0x1 }, > + { 0x100a2, 0x2 }, > + { 0x100a3, 0x3 }, > + { 0x100a4, 0x4 }, > + { 0x100a5, 0x5 }, > + { 0x100a6, 0x6 }, > + { 0x100a7, 0x7 }, > + { 0x110a0, 0x0 }, > + { 0x110a1, 0x1 }, > + { 0x110a2, 0x3 }, > + { 0x110a3, 0x4 }, > + { 0x110a4, 0x5 }, > + { 0x110a5, 0x2 }, > + { 0x110a6, 0x7 }, > + { 0x110a7, 0x6 }, > + { 0x120a0, 0x0 }, > + { 0x120a1, 0x1 }, > + { 0x120a2, 0x3 }, > + { 0x120a3, 0x2 }, > + { 0x120a4, 0x5 }, > + { 0x120a5, 0x4 }, > + { 0x120a6, 0x7 }, > + { 0x120a7, 0x6 }, > + { 0x130a0, 0x0 }, > + { 0x130a1, 0x1 }, > + { 0x130a2, 0x2 }, > + { 0x130a3, 0x3 }, > + { 0x130a4, 0x4 }, > + { 0x130a5, 0x5 }, > + { 0x130a6, 0x6 }, > + { 0x130a7, 0x7 }, > + { 0x1005f, 0x1ff }, > + { 0x1015f, 0x1ff }, > + { 0x1105f, 0x1ff }, > + { 0x1115f, 0x1ff }, > + { 0x1205f, 0x1ff }, > + { 0x1215f, 0x1ff }, > + { 0x1305f, 0x1ff }, > + { 0x1315f, 0x1ff }, > + { 0x11005f, 0x1ff }, > + { 0x11015f, 0x1ff }, > + { 0x11105f, 0x1ff }, > + { 0x11115f, 0x1ff }, > + { 0x11205f, 0x1ff }, > + { 0x11215f, 0x1ff }, > + { 0x11305f, 0x1ff }, > + { 0x11315f, 0x1ff }, > + { 0x21005f, 0x1ff }, > + { 0x21015f, 0x1ff }, > + { 0x21105f, 0x1ff }, > + { 0x21115f, 0x1ff }, > + { 0x21205f, 0x1ff }, > + { 0x21215f, 0x1ff }, > + { 0x21305f, 0x1ff }, > + { 0x21315f, 0x1ff }, > + { 0x55, 0x1ff }, > + { 0x1055, 0x1ff }, > + { 0x2055, 0x1ff }, > + { 0x3055, 0x1ff }, > + { 0x4055, 0x1ff }, > + { 0x5055, 0x1ff }, > + { 0x6055, 0x1ff }, > + { 0x7055, 0x1ff }, > + { 0x8055, 0x1ff }, > + { 0x9055, 0x1ff }, > + { 0x200c5, 0x19 }, > + { 0x1200c5, 0x7 }, > + { 0x2200c5, 0x7 }, > + { 0x2002e, 0x2 }, > + { 0x12002e, 0x2 }, > + { 0x22002e, 0x2 }, > + { 0x90204, 0x0 }, > + { 0x190204, 0x0 }, > + { 0x290204, 0x0 }, > + { 0x20024, 0x1e3 }, > + { 0x2003a, 0x2 }, > + { 0x120024, 0x1e3 }, > + { 0x2003a, 0x2 }, > + { 0x220024, 0x1e3 }, > + { 0x2003a, 0x2 }, > + { 0x20056, 0x3 }, > + { 0x120056, 0x3 }, > + { 0x220056, 0x3 }, > + { 0x1004d, 0xe00 }, > + { 0x1014d, 0xe00 }, > + { 0x1104d, 0xe00 }, > + { 0x1114d, 0xe00 }, > + { 0x1204d, 0xe00 }, > + { 0x1214d, 0xe00 }, > + { 0x1304d, 0xe00 }, > + { 0x1314d, 0xe00 }, > + { 0x11004d, 0xe00 }, > + { 0x11014d, 0xe00 }, > + { 0x11104d, 0xe00 }, > + { 0x11114d, 0xe00 }, > + { 0x11204d, 0xe00 }, > + { 0x11214d, 0xe00 }, > + { 0x11304d, 0xe00 }, > + { 0x11314d, 0xe00 }, > + { 0x21004d, 0xe00 }, > + { 0x21014d, 0xe00 }, > + { 0x21104d, 0xe00 }, > + { 0x21114d, 0xe00 }, > + { 0x21204d, 0xe00 }, > + { 0x21214d, 0xe00 }, > + { 0x21304d, 0xe00 }, > + { 0x21314d, 0xe00 }, > + { 0x10049, 0xeba }, > + { 0x10149, 0xeba }, > + { 0x11049, 0xeba }, > + { 0x11149, 0xeba }, > + { 0x12049, 0xeba }, > + { 0x12149, 0xeba }, > + { 0x13049, 0xeba }, > + { 0x13149, 0xeba }, > + { 0x110049, 0xeba }, > + { 0x110149, 0xeba }, > + { 0x111049, 0xeba }, > + { 0x111149, 0xeba }, > + { 0x112049, 0xeba }, > + { 0x112149, 0xeba }, > + { 0x113049, 0xeba }, > + { 0x113149, 0xeba }, > + { 0x210049, 0xeba }, > + { 0x210149, 0xeba }, > + { 0x211049, 0xeba }, > + { 0x211149, 0xeba }, > + { 0x212049, 0xeba }, > + { 0x212149, 0xeba }, > + { 0x213049, 0xeba }, > + { 0x213149, 0xeba }, > + { 0x43, 0x63 }, > + { 0x1043, 0x63 }, > + { 0x2043, 0x63 }, > + { 0x3043, 0x63 }, > + { 0x4043, 0x63 }, > + { 0x5043, 0x63 }, > + { 0x6043, 0x63 }, > + { 0x7043, 0x63 }, > + { 0x8043, 0x63 }, > + { 0x9043, 0x63 }, > + { 0x20018, 0x3 }, > + { 0x20075, 0x4 }, > + { 0x20050, 0x0 }, > + { 0x20008, 0x2ee }, > + { 0x120008, 0x64 }, > + { 0x220008, 0x19 }, > + { 0x20088, 0x9 }, > + { 0x200b2, 0x104 }, > + { 0x10043, 0x5a1 }, > + { 0x10143, 0x5a1 }, > + { 0x11043, 0x5a1 }, > + { 0x11143, 0x5a1 }, > + { 0x12043, 0x5a1 }, > + { 0x12143, 0x5a1 }, > + { 0x13043, 0x5a1 }, > + { 0x13143, 0x5a1 }, > + { 0x1200b2, 0x104 }, > + { 0x110043, 0x5a1 }, > + { 0x110143, 0x5a1 }, > + { 0x111043, 0x5a1 }, > + { 0x111143, 0x5a1 }, > + { 0x112043, 0x5a1 }, > + { 0x112143, 0x5a1 }, > + { 0x113043, 0x5a1 }, > + { 0x113143, 0x5a1 }, > + { 0x2200b2, 0x104 }, > + { 0x210043, 0x5a1 }, > + { 0x210143, 0x5a1 }, > + { 0x211043, 0x5a1 }, > + { 0x211143, 0x5a1 }, > + { 0x212043, 0x5a1 }, > + { 0x212143, 0x5a1 }, > + { 0x213043, 0x5a1 }, > + { 0x213143, 0x5a1 }, > + { 0x200fa, 0x1 }, > + { 0x1200fa, 0x1 }, > + { 0x2200fa, 0x1 }, > + { 0x20019, 0x1 }, > + { 0x120019, 0x1 }, > + { 0x220019, 0x1 }, > + { 0x200f0, 0x660 }, > + { 0x200f1, 0x0 }, > + { 0x200f2, 0x4444 }, > + { 0x200f3, 0x8888 }, > + { 0x200f4, 0x5665 }, > + { 0x200f5, 0x0 }, > + { 0x200f6, 0x0 }, > + { 0x200f7, 0xf000 }, > + { 0x20025, 0x0 }, > + { 0x2002d, 0x0 }, > + { 0x12002d, 0x0 }, > + { 0x22002d, 0x0 }, > + { 0x2007d, 0x212 }, > + { 0x12007d, 0x212 }, > + { 0x22007d, 0x212 }, > + { 0x2007c, 0x61 }, > + { 0x12007c, 0x61 }, > + { 0x22007c, 0x61 }, > + { 0x1004a, 0x500 }, > + { 0x1104a, 0x500 }, > + { 0x1204a, 0x500 }, > + { 0x1304a, 0x500 }, > + { 0x2002c, 0x0 }, > +}; > + > +/* ddr phy trained csr */ > +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { > + { 0x200b2, 0x0 }, > + { 0x1200b2, 0x0 }, > + { 0x2200b2, 0x0 }, > + { 0x200cb, 0x0 }, > + { 0x10043, 0x0 }, > + { 0x110043, 0x0 }, > + { 0x210043, 0x0 }, > + { 0x10143, 0x0 }, > + { 0x110143, 0x0 }, > + { 0x210143, 0x0 }, > + { 0x11043, 0x0 }, > + { 0x111043, 0x0 }, > + { 0x211043, 0x0 }, > + { 0x11143, 0x0 }, > + { 0x111143, 0x0 }, > + { 0x211143, 0x0 }, > + { 0x12043, 0x0 }, > + { 0x112043, 0x0 }, > + { 0x212043, 0x0 }, > + { 0x12143, 0x0 }, > + { 0x112143, 0x0 }, > + { 0x212143, 0x0 }, > + { 0x13043, 0x0 }, > + { 0x113043, 0x0 }, > + { 0x213043, 0x0 }, > + { 0x13143, 0x0 }, > + { 0x113143, 0x0 }, > + { 0x213143, 0x0 }, > + { 0x80, 0x0 }, > + { 0x100080, 0x0 }, > + { 0x200080, 0x0 }, > + { 0x1080, 0x0 }, > + { 0x101080, 0x0 }, > + { 0x201080, 0x0 }, > + { 0x2080, 0x0 }, > + { 0x102080, 0x0 }, > + { 0x202080, 0x0 }, > + { 0x3080, 0x0 }, > + { 0x103080, 0x0 }, > + { 0x203080, 0x0 }, > + { 0x4080, 0x0 }, > + { 0x104080, 0x0 }, > + { 0x204080, 0x0 }, > + { 0x5080, 0x0 }, > + { 0x105080, 0x0 }, > + { 0x205080, 0x0 }, > + { 0x6080, 0x0 }, > + { 0x106080, 0x0 }, > + { 0x206080, 0x0 }, > + { 0x7080, 0x0 }, > + { 0x107080, 0x0 }, > + { 0x207080, 0x0 }, > + { 0x8080, 0x0 }, > + { 0x108080, 0x0 }, > + { 0x208080, 0x0 }, > + { 0x9080, 0x0 }, > + { 0x109080, 0x0 }, > + { 0x209080, 0x0 }, > + { 0x10080, 0x0 }, > + { 0x110080, 0x0 }, > + { 0x210080, 0x0 }, > + { 0x10180, 0x0 }, > + { 0x110180, 0x0 }, > + { 0x210180, 0x0 }, > + { 0x11080, 0x0 }, > + { 0x111080, 0x0 }, > + { 0x211080, 0x0 }, > + { 0x11180, 0x0 }, > + { 0x111180, 0x0 }, > + { 0x211180, 0x0 }, > + { 0x12080, 0x0 }, > + { 0x112080, 0x0 }, > + { 0x212080, 0x0 }, > + { 0x12180, 0x0 }, > + { 0x112180, 0x0 }, > + { 0x212180, 0x0 }, > + { 0x13080, 0x0 }, > + { 0x113080, 0x0 }, > + { 0x213080, 0x0 }, > + { 0x13180, 0x0 }, > + { 0x113180, 0x0 }, > + { 0x213180, 0x0 }, > + { 0x10081, 0x0 }, > + { 0x110081, 0x0 }, > + { 0x210081, 0x0 }, > + { 0x10181, 0x0 }, > + { 0x110181, 0x0 }, > + { 0x210181, 0x0 }, > + { 0x11081, 0x0 }, > + { 0x111081, 0x0 }, > + { 0x211081, 0x0 }, > + { 0x11181, 0x0 }, > + { 0x111181, 0x0 }, > + { 0x211181, 0x0 }, > + { 0x12081, 0x0 }, > + { 0x112081, 0x0 }, > + { 0x212081, 0x0 }, > + { 0x12181, 0x0 }, > + { 0x112181, 0x0 }, > + { 0x212181, 0x0 }, > + { 0x13081, 0x0 }, > + { 0x113081, 0x0 }, > + { 0x213081, 0x0 }, > + { 0x13181, 0x0 }, > + { 0x113181, 0x0 }, > + { 0x213181, 0x0 }, > + { 0x100d0, 0x0 }, > + { 0x1100d0, 0x0 }, > + { 0x2100d0, 0x0 }, > + { 0x101d0, 0x0 }, > + { 0x1101d0, 0x0 }, > + { 0x2101d0, 0x0 }, > + { 0x110d0, 0x0 }, > + { 0x1110d0, 0x0 }, > + { 0x2110d0, 0x0 }, > + { 0x111d0, 0x0 }, > + { 0x1111d0, 0x0 }, > + { 0x2111d0, 0x0 }, > + { 0x120d0, 0x0 }, > + { 0x1120d0, 0x0 }, > + { 0x2120d0, 0x0 }, > + { 0x121d0, 0x0 }, > + { 0x1121d0, 0x0 }, > + { 0x2121d0, 0x0 }, > + { 0x130d0, 0x0 }, > + { 0x1130d0, 0x0 }, > + { 0x2130d0, 0x0 }, > + { 0x131d0, 0x0 }, > + { 0x1131d0, 0x0 }, > + { 0x2131d0, 0x0 }, > + { 0x100d1, 0x0 }, > + { 0x1100d1, 0x0 }, > + { 0x2100d1, 0x0 }, > + { 0x101d1, 0x0 }, > + { 0x1101d1, 0x0 }, > + { 0x2101d1, 0x0 }, > + { 0x110d1, 0x0 }, > + { 0x1110d1, 0x0 }, > + { 0x2110d1, 0x0 }, > + { 0x111d1, 0x0 }, > + { 0x1111d1, 0x0 }, > + { 0x2111d1, 0x0 }, > + { 0x120d1, 0x0 }, > + { 0x1120d1, 0x0 }, > + { 0x2120d1, 0x0 }, > + { 0x121d1, 0x0 }, > + { 0x1121d1, 0x0 }, > + { 0x2121d1, 0x0 }, > + { 0x130d1, 0x0 }, > + { 0x1130d1, 0x0 }, > + { 0x2130d1, 0x0 }, > + { 0x131d1, 0x0 }, > + { 0x1131d1, 0x0 }, > + { 0x2131d1, 0x0 }, > + { 0x10068, 0x0 }, > + { 0x10168, 0x0 }, > + { 0x10268, 0x0 }, > + { 0x10368, 0x0 }, > + { 0x10468, 0x0 }, > + { 0x10568, 0x0 }, > + { 0x10668, 0x0 }, > + { 0x10768, 0x0 }, > + { 0x10868, 0x0 }, > + { 0x11068, 0x0 }, > + { 0x11168, 0x0 }, > + { 0x11268, 0x0 }, > + { 0x11368, 0x0 }, > + { 0x11468, 0x0 }, > + { 0x11568, 0x0 }, > + { 0x11668, 0x0 }, > + { 0x11768, 0x0 }, > + { 0x11868, 0x0 }, > + { 0x12068, 0x0 }, > + { 0x12168, 0x0 }, > + { 0x12268, 0x0 }, > + { 0x12368, 0x0 }, > + { 0x12468, 0x0 }, > + { 0x12568, 0x0 }, > + { 0x12668, 0x0 }, > + { 0x12768, 0x0 }, > + { 0x12868, 0x0 }, > + { 0x13068, 0x0 }, > + { 0x13168, 0x0 }, > + { 0x13268, 0x0 }, > + { 0x13368, 0x0 }, > + { 0x13468, 0x0 }, > + { 0x13568, 0x0 }, > + { 0x13668, 0x0 }, > + { 0x13768, 0x0 }, > + { 0x13868, 0x0 }, > + { 0x10069, 0x0 }, > + { 0x10169, 0x0 }, > + { 0x10269, 0x0 }, > + { 0x10369, 0x0 }, > + { 0x10469, 0x0 }, > + { 0x10569, 0x0 }, > + { 0x10669, 0x0 }, > + { 0x10769, 0x0 }, > + { 0x10869, 0x0 }, > + { 0x11069, 0x0 }, > + { 0x11169, 0x0 }, > + { 0x11269, 0x0 }, > + { 0x11369, 0x0 }, > + { 0x11469, 0x0 }, > + { 0x11569, 0x0 }, > + { 0x11669, 0x0 }, > + { 0x11769, 0x0 }, > + { 0x11869, 0x0 }, > + { 0x12069, 0x0 }, > + { 0x12169, 0x0 }, > + { 0x12269, 0x0 }, > + { 0x12369, 0x0 }, > + { 0x12469, 0x0 }, > + { 0x12569, 0x0 }, > + { 0x12669, 0x0 }, > + { 0x12769, 0x0 }, > + { 0x12869, 0x0 }, > + { 0x13069, 0x0 }, > + { 0x13169, 0x0 }, > + { 0x13269, 0x0 }, > + { 0x13369, 0x0 }, > + { 0x13469, 0x0 }, > + { 0x13569, 0x0 }, > + { 0x13669, 0x0 }, > + { 0x13769, 0x0 }, > + { 0x13869, 0x0 }, > + { 0x1008c, 0x0 }, > + { 0x11008c, 0x0 }, > + { 0x21008c, 0x0 }, > + { 0x1018c, 0x0 }, > + { 0x11018c, 0x0 }, > + { 0x21018c, 0x0 }, > + { 0x1108c, 0x0 }, > + { 0x11108c, 0x0 }, > + { 0x21108c, 0x0 }, > + { 0x1118c, 0x0 }, > + { 0x11118c, 0x0 }, > + { 0x21118c, 0x0 }, > + { 0x1208c, 0x0 }, > + { 0x11208c, 0x0 }, > + { 0x21208c, 0x0 }, > + { 0x1218c, 0x0 }, > + { 0x11218c, 0x0 }, > + { 0x21218c, 0x0 }, > + { 0x1308c, 0x0 }, > + { 0x11308c, 0x0 }, > + { 0x21308c, 0x0 }, > + { 0x1318c, 0x0 }, > + { 0x11318c, 0x0 }, > + { 0x21318c, 0x0 }, > + { 0x1008d, 0x0 }, > + { 0x11008d, 0x0 }, > + { 0x21008d, 0x0 }, > + { 0x1018d, 0x0 }, > + { 0x11018d, 0x0 }, > + { 0x21018d, 0x0 }, > + { 0x1108d, 0x0 }, > + { 0x11108d, 0x0 }, > + { 0x21108d, 0x0 }, > + { 0x1118d, 0x0 }, > + { 0x11118d, 0x0 }, > + { 0x21118d, 0x0 }, > + { 0x1208d, 0x0 }, > + { 0x11208d, 0x0 }, > + { 0x21208d, 0x0 }, > + { 0x1218d, 0x0 }, > + { 0x11218d, 0x0 }, > + { 0x21218d, 0x0 }, > + { 0x1308d, 0x0 }, > + { 0x11308d, 0x0 }, > + { 0x21308d, 0x0 }, > + { 0x1318d, 0x0 }, > + { 0x11318d, 0x0 }, > + { 0x21318d, 0x0 }, > + { 0x100c0, 0x0 }, > + { 0x1100c0, 0x0 }, > + { 0x2100c0, 0x0 }, > + { 0x101c0, 0x0 }, > + { 0x1101c0, 0x0 }, > + { 0x2101c0, 0x0 }, > + { 0x102c0, 0x0 }, > + { 0x1102c0, 0x0 }, > + { 0x2102c0, 0x0 }, > + { 0x103c0, 0x0 }, > + { 0x1103c0, 0x0 }, > + { 0x2103c0, 0x0 }, > + { 0x104c0, 0x0 }, > + { 0x1104c0, 0x0 }, > + { 0x2104c0, 0x0 }, > + { 0x105c0, 0x0 }, > + { 0x1105c0, 0x0 }, > + { 0x2105c0, 0x0 }, > + { 0x106c0, 0x0 }, > + { 0x1106c0, 0x0 }, > + { 0x2106c0, 0x0 }, > + { 0x107c0, 0x0 }, > + { 0x1107c0, 0x0 }, > + { 0x2107c0, 0x0 }, > + { 0x108c0, 0x0 }, > + { 0x1108c0, 0x0 }, > + { 0x2108c0, 0x0 }, > + { 0x110c0, 0x0 }, > + { 0x1110c0, 0x0 }, > + { 0x2110c0, 0x0 }, > + { 0x111c0, 0x0 }, > + { 0x1111c0, 0x0 }, > + { 0x2111c0, 0x0 }, > + { 0x112c0, 0x0 }, > + { 0x1112c0, 0x0 }, > + { 0x2112c0, 0x0 }, > + { 0x113c0, 0x0 }, > + { 0x1113c0, 0x0 }, > + { 0x2113c0, 0x0 }, > + { 0x114c0, 0x0 }, > + { 0x1114c0, 0x0 }, > + { 0x2114c0, 0x0 }, > + { 0x115c0, 0x0 }, > + { 0x1115c0, 0x0 }, > + { 0x2115c0, 0x0 }, > + { 0x116c0, 0x0 }, > + { 0x1116c0, 0x0 }, > + { 0x2116c0, 0x0 }, > + { 0x117c0, 0x0 }, > + { 0x1117c0, 0x0 }, > + { 0x2117c0, 0x0 }, > + { 0x118c0, 0x0 }, > + { 0x1118c0, 0x0 }, > + { 0x2118c0, 0x0 }, > + { 0x120c0, 0x0 }, > + { 0x1120c0, 0x0 }, > + { 0x2120c0, 0x0 }, > + { 0x121c0, 0x0 }, > + { 0x1121c0, 0x0 }, > + { 0x2121c0, 0x0 }, > + { 0x122c0, 0x0 }, > + { 0x1122c0, 0x0 }, > + { 0x2122c0, 0x0 }, > + { 0x123c0, 0x0 }, > + { 0x1123c0, 0x0 }, > + { 0x2123c0, 0x0 }, > + { 0x124c0, 0x0 }, > + { 0x1124c0, 0x0 }, > + { 0x2124c0, 0x0 }, > + { 0x125c0, 0x0 }, > + { 0x1125c0, 0x0 }, > + { 0x2125c0, 0x0 }, > + { 0x126c0, 0x0 }, > + { 0x1126c0, 0x0 }, > + { 0x2126c0, 0x0 }, > + { 0x127c0, 0x0 }, > + { 0x1127c0, 0x0 }, > + { 0x2127c0, 0x0 }, > + { 0x128c0, 0x0 }, > + { 0x1128c0, 0x0 }, > + { 0x2128c0, 0x0 }, > + { 0x130c0, 0x0 }, > + { 0x1130c0, 0x0 }, > + { 0x2130c0, 0x0 }, > + { 0x131c0, 0x0 }, > + { 0x1131c0, 0x0 }, > + { 0x2131c0, 0x0 }, > + { 0x132c0, 0x0 }, > + { 0x1132c0, 0x0 }, > + { 0x2132c0, 0x0 }, > + { 0x133c0, 0x0 }, > + { 0x1133c0, 0x0 }, > + { 0x2133c0, 0x0 }, > + { 0x134c0, 0x0 }, > + { 0x1134c0, 0x0 }, > + { 0x2134c0, 0x0 }, > + { 0x135c0, 0x0 }, > + { 0x1135c0, 0x0 }, > + { 0x2135c0, 0x0 }, > + { 0x136c0, 0x0 }, > + { 0x1136c0, 0x0 }, > + { 0x2136c0, 0x0 }, > + { 0x137c0, 0x0 }, > + { 0x1137c0, 0x0 }, > + { 0x2137c0, 0x0 }, > + { 0x138c0, 0x0 }, > + { 0x1138c0, 0x0 }, > + { 0x2138c0, 0x0 }, > + { 0x100c1, 0x0 }, > + { 0x1100c1, 0x0 }, > + { 0x2100c1, 0x0 }, > + { 0x101c1, 0x0 }, > + { 0x1101c1, 0x0 }, > + { 0x2101c1, 0x0 }, > + { 0x102c1, 0x0 }, > + { 0x1102c1, 0x0 }, > + { 0x2102c1, 0x0 }, > + { 0x103c1, 0x0 }, > + { 0x1103c1, 0x0 }, > + { 0x2103c1, 0x0 }, > + { 0x104c1, 0x0 }, > + { 0x1104c1, 0x0 }, > + { 0x2104c1, 0x0 }, > + { 0x105c1, 0x0 }, > + { 0x1105c1, 0x0 }, > + { 0x2105c1, 0x0 }, > + { 0x106c1, 0x0 }, > + { 0x1106c1, 0x0 }, > + { 0x2106c1, 0x0 }, > + { 0x107c1, 0x0 }, > + { 0x1107c1, 0x0 }, > + { 0x2107c1, 0x0 }, > + { 0x108c1, 0x0 }, > + { 0x1108c1, 0x0 }, > + { 0x2108c1, 0x0 }, > + { 0x110c1, 0x0 }, > + { 0x1110c1, 0x0 }, > + { 0x2110c1, 0x0 }, > + { 0x111c1, 0x0 }, > + { 0x1111c1, 0x0 }, > + { 0x2111c1, 0x0 }, > + { 0x112c1, 0x0 }, > + { 0x1112c1, 0x0 }, > + { 0x2112c1, 0x0 }, > + { 0x113c1, 0x0 }, > + { 0x1113c1, 0x0 }, > + { 0x2113c1, 0x0 }, > + { 0x114c1, 0x0 }, > + { 0x1114c1, 0x0 }, > + { 0x2114c1, 0x0 }, > + { 0x115c1, 0x0 }, > + { 0x1115c1, 0x0 }, > + { 0x2115c1, 0x0 }, > + { 0x116c1, 0x0 }, > + { 0x1116c1, 0x0 }, > + { 0x2116c1, 0x0 }, > + { 0x117c1, 0x0 }, > + { 0x1117c1, 0x0 }, > + { 0x2117c1, 0x0 }, > + { 0x118c1, 0x0 }, > + { 0x1118c1, 0x0 }, > + { 0x2118c1, 0x0 }, > + { 0x120c1, 0x0 }, > + { 0x1120c1, 0x0 }, > + { 0x2120c1, 0x0 }, > + { 0x121c1, 0x0 }, > + { 0x1121c1, 0x0 }, > + { 0x2121c1, 0x0 }, > + { 0x122c1, 0x0 }, > + { 0x1122c1, 0x0 }, > + { 0x2122c1, 0x0 }, > + { 0x123c1, 0x0 }, > + { 0x1123c1, 0x0 }, > + { 0x2123c1, 0x0 }, > + { 0x124c1, 0x0 }, > + { 0x1124c1, 0x0 }, > + { 0x2124c1, 0x0 }, > + { 0x125c1, 0x0 }, > + { 0x1125c1, 0x0 }, > + { 0x2125c1, 0x0 }, > + { 0x126c1, 0x0 }, > + { 0x1126c1, 0x0 }, > + { 0x2126c1, 0x0 }, > + { 0x127c1, 0x0 }, > + { 0x1127c1, 0x0 }, > + { 0x2127c1, 0x0 }, > + { 0x128c1, 0x0 }, > + { 0x1128c1, 0x0 }, > + { 0x2128c1, 0x0 }, > + { 0x130c1, 0x0 }, > + { 0x1130c1, 0x0 }, > + { 0x2130c1, 0x0 }, > + { 0x131c1, 0x0 }, > + { 0x1131c1, 0x0 }, > + { 0x2131c1, 0x0 }, > + { 0x132c1, 0x0 }, > + { 0x1132c1, 0x0 }, > + { 0x2132c1, 0x0 }, > + { 0x133c1, 0x0 }, > + { 0x1133c1, 0x0 }, > + { 0x2133c1, 0x0 }, > + { 0x134c1, 0x0 }, > + { 0x1134c1, 0x0 }, > + { 0x2134c1, 0x0 }, > + { 0x135c1, 0x0 }, > + { 0x1135c1, 0x0 }, > + { 0x2135c1, 0x0 }, > + { 0x136c1, 0x0 }, > + { 0x1136c1, 0x0 }, > + { 0x2136c1, 0x0 }, > + { 0x137c1, 0x0 }, > + { 0x1137c1, 0x0 }, > + { 0x2137c1, 0x0 }, > + { 0x138c1, 0x0 }, > + { 0x1138c1, 0x0 }, > + { 0x2138c1, 0x0 }, > + { 0x10020, 0x0 }, > + { 0x110020, 0x0 }, > + { 0x210020, 0x0 }, > + { 0x11020, 0x0 }, > + { 0x111020, 0x0 }, > + { 0x211020, 0x0 }, > + { 0x12020, 0x0 }, > + { 0x112020, 0x0 }, > + { 0x212020, 0x0 }, > + { 0x13020, 0x0 }, > + { 0x113020, 0x0 }, > + { 0x213020, 0x0 }, > + { 0x20072, 0x0 }, > + { 0x20073, 0x0 }, > + { 0x20074, 0x0 }, > + { 0x100aa, 0x0 }, > + { 0x110aa, 0x0 }, > + { 0x120aa, 0x0 }, > + { 0x130aa, 0x0 }, > + { 0x20010, 0x0 }, > + { 0x120010, 0x0 }, > + { 0x220010, 0x0 }, > + { 0x20011, 0x0 }, > + { 0x120011, 0x0 }, > + { 0x220011, 0x0 }, > + { 0x100ae, 0x0 }, > + { 0x1100ae, 0x0 }, > + { 0x2100ae, 0x0 }, > + { 0x100af, 0x0 }, > + { 0x1100af, 0x0 }, > + { 0x2100af, 0x0 }, > + { 0x110ae, 0x0 }, > + { 0x1110ae, 0x0 }, > + { 0x2110ae, 0x0 }, > + { 0x110af, 0x0 }, > + { 0x1110af, 0x0 }, > + { 0x2110af, 0x0 }, > + { 0x120ae, 0x0 }, > + { 0x1120ae, 0x0 }, > + { 0x2120ae, 0x0 }, > + { 0x120af, 0x0 }, > + { 0x1120af, 0x0 }, > + { 0x2120af, 0x0 }, > + { 0x130ae, 0x0 }, > + { 0x1130ae, 0x0 }, > + { 0x2130ae, 0x0 }, > + { 0x130af, 0x0 }, > + { 0x1130af, 0x0 }, > + { 0x2130af, 0x0 }, > + { 0x20020, 0x0 }, > + { 0x120020, 0x0 }, > + { 0x220020, 0x0 }, > + { 0x100a0, 0x0 }, > + { 0x100a1, 0x0 }, > + { 0x100a2, 0x0 }, > + { 0x100a3, 0x0 }, > + { 0x100a4, 0x0 }, > + { 0x100a5, 0x0 }, > + { 0x100a6, 0x0 }, > + { 0x100a7, 0x0 }, > + { 0x110a0, 0x0 }, > + { 0x110a1, 0x0 }, > + { 0x110a2, 0x0 }, > + { 0x110a3, 0x0 }, > + { 0x110a4, 0x0 }, > + { 0x110a5, 0x0 }, > + { 0x110a6, 0x0 }, > + { 0x110a7, 0x0 }, > + { 0x120a0, 0x0 }, > + { 0x120a1, 0x0 }, > + { 0x120a2, 0x0 }, > + { 0x120a3, 0x0 }, > + { 0x120a4, 0x0 }, > + { 0x120a5, 0x0 }, > + { 0x120a6, 0x0 }, > + { 0x120a7, 0x0 }, > + { 0x130a0, 0x0 }, > + { 0x130a1, 0x0 }, > + { 0x130a2, 0x0 }, > + { 0x130a3, 0x0 }, > + { 0x130a4, 0x0 }, > + { 0x130a5, 0x0 }, > + { 0x130a6, 0x0 }, > + { 0x130a7, 0x0 }, > + { 0x2007c, 0x0 }, > + { 0x12007c, 0x0 }, > + { 0x22007c, 0x0 }, > + { 0x2007d, 0x0 }, > + { 0x12007d, 0x0 }, > + { 0x22007d, 0x0 }, > + { 0x400fd, 0x0 }, > + { 0x400c0, 0x0 }, > + { 0x90201, 0x0 }, > + { 0x190201, 0x0 }, > + { 0x290201, 0x0 }, > + { 0x90202, 0x0 }, > + { 0x190202, 0x0 }, > + { 0x290202, 0x0 }, > + { 0x90203, 0x0 }, > + { 0x190203, 0x0 }, > + { 0x290203, 0x0 }, > + { 0x90204, 0x0 }, > + { 0x190204, 0x0 }, > + { 0x290204, 0x0 }, > + { 0x90205, 0x0 }, > + { 0x190205, 0x0 }, > + { 0x290205, 0x0 }, > + { 0x90206, 0x0 }, > + { 0x190206, 0x0 }, > + { 0x290206, 0x0 }, > + { 0x90207, 0x0 }, > + { 0x190207, 0x0 }, > + { 0x290207, 0x0 }, > + { 0x90208, 0x0 }, > + { 0x190208, 0x0 }, > + { 0x290208, 0x0 }, > + { 0x10062, 0x0 }, > + { 0x10162, 0x0 }, > + { 0x10262, 0x0 }, > + { 0x10362, 0x0 }, > + { 0x10462, 0x0 }, > + { 0x10562, 0x0 }, > + { 0x10662, 0x0 }, > + { 0x10762, 0x0 }, > + { 0x10862, 0x0 }, > + { 0x11062, 0x0 }, > + { 0x11162, 0x0 }, > + { 0x11262, 0x0 }, > + { 0x11362, 0x0 }, > + { 0x11462, 0x0 }, > + { 0x11562, 0x0 }, > + { 0x11662, 0x0 }, > + { 0x11762, 0x0 }, > + { 0x11862, 0x0 }, > + { 0x12062, 0x0 }, > + { 0x12162, 0x0 }, > + { 0x12262, 0x0 }, > + { 0x12362, 0x0 }, > + { 0x12462, 0x0 }, > + { 0x12562, 0x0 }, > + { 0x12662, 0x0 }, > + { 0x12762, 0x0 }, > + { 0x12862, 0x0 }, > + { 0x13062, 0x0 }, > + { 0x13162, 0x0 }, > + { 0x13262, 0x0 }, > + { 0x13362, 0x0 }, > + { 0x13462, 0x0 }, > + { 0x13562, 0x0 }, > + { 0x13662, 0x0 }, > + { 0x13762, 0x0 }, > + { 0x13862, 0x0 }, > + { 0x20077, 0x0 }, > + { 0x10001, 0x0 }, > + { 0x11001, 0x0 }, > + { 0x12001, 0x0 }, > + { 0x13001, 0x0 }, > + { 0x10040, 0x0 }, > + { 0x10140, 0x0 }, > + { 0x10240, 0x0 }, > + { 0x10340, 0x0 }, > + { 0x10440, 0x0 }, > + { 0x10540, 0x0 }, > + { 0x10640, 0x0 }, > + { 0x10740, 0x0 }, > + { 0x10840, 0x0 }, > + { 0x10030, 0x0 }, > + { 0x10130, 0x0 }, > + { 0x10230, 0x0 }, > + { 0x10330, 0x0 }, > + { 0x10430, 0x0 }, > + { 0x10530, 0x0 }, > + { 0x10630, 0x0 }, > + { 0x10730, 0x0 }, > + { 0x10830, 0x0 }, > + { 0x11040, 0x0 }, > + { 0x11140, 0x0 }, > + { 0x11240, 0x0 }, > + { 0x11340, 0x0 }, > + { 0x11440, 0x0 }, > + { 0x11540, 0x0 }, > + { 0x11640, 0x0 }, > + { 0x11740, 0x0 }, > + { 0x11840, 0x0 }, > + { 0x11030, 0x0 }, > + { 0x11130, 0x0 }, > + { 0x11230, 0x0 }, > + { 0x11330, 0x0 }, > + { 0x11430, 0x0 }, > + { 0x11530, 0x0 }, > + { 0x11630, 0x0 }, > + { 0x11730, 0x0 }, > + { 0x11830, 0x0 }, > + { 0x12040, 0x0 }, > + { 0x12140, 0x0 }, > + { 0x12240, 0x0 }, > + { 0x12340, 0x0 }, > + { 0x12440, 0x0 }, > + { 0x12540, 0x0 }, > + { 0x12640, 0x0 }, > + { 0x12740, 0x0 }, > + { 0x12840, 0x0 }, > + { 0x12030, 0x0 }, > + { 0x12130, 0x0 }, > + { 0x12230, 0x0 }, > + { 0x12330, 0x0 }, > + { 0x12430, 0x0 }, > + { 0x12530, 0x0 }, > + { 0x12630, 0x0 }, > + { 0x12730, 0x0 }, > + { 0x12830, 0x0 }, > + { 0x13040, 0x0 }, > + { 0x13140, 0x0 }, > + { 0x13240, 0x0 }, > + { 0x13340, 0x0 }, > + { 0x13440, 0x0 }, > + { 0x13540, 0x0 }, > + { 0x13640, 0x0 }, > + { 0x13740, 0x0 }, > + { 0x13840, 0x0 }, > + { 0x13030, 0x0 }, > + { 0x13130, 0x0 }, > + { 0x13230, 0x0 }, > + { 0x13330, 0x0 }, > + { 0x13430, 0x0 }, > + { 0x13530, 0x0 }, > + { 0x13630, 0x0 }, > + { 0x13730, 0x0 }, > + { 0x13830, 0x0 }, > +}; > + > +/* P0 message block paremeter for training firmware */ > +static struct dram_cfg_param ddr_fsp0_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54003, 0xbb8 }, > + { 0x54004, 0x2 }, > + { 0x54005, 0x2228 }, > + { 0x54006, 0x14 }, > + { 0x54008, 0x131f }, > + { 0x54009, 0xc8 }, > + { 0x5400b, 0x2 }, > + { 0x5400f, 0x100 }, > + { 0x54012, 0x110 }, > + { 0x54019, 0x2dd4 }, > + { 0x5401a, 0x33 }, > + { 0x5401b, 0x4866 }, > + { 0x5401c, 0x4800 }, > + { 0x5401e, 0x16 }, > + { 0x5401f, 0x2dd4 }, > + { 0x54020, 0x33 }, > + { 0x54021, 0x4866 }, > + { 0x54022, 0x4800 }, > + { 0x54024, 0x16 }, > + { 0x5402b, 0x1000 }, > + { 0x5402c, 0x1 }, > + { 0x54032, 0xd400 }, > + { 0x54033, 0x332d }, > + { 0x54034, 0x6600 }, > + { 0x54035, 0x48 }, > + { 0x54036, 0x48 }, > + { 0x54037, 0x1600 }, > + { 0x54038, 0xd400 }, > + { 0x54039, 0x332d }, > + { 0x5403a, 0x6600 }, > + { 0x5403b, 0x48 }, > + { 0x5403c, 0x48 }, > + { 0x5403d, 0x1600 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* P1 message block paremeter for training firmware */ > +static struct dram_cfg_param ddr_fsp1_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54002, 0x101 }, > + { 0x54003, 0x190 }, > + { 0x54004, 0x2 }, > + { 0x54005, 0x2228 }, > + { 0x54006, 0x14 }, > + { 0x54008, 0x121f }, > + { 0x54009, 0xc8 }, > + { 0x5400b, 0x2 }, > + { 0x5400f, 0x100 }, > + { 0x54012, 0x110 }, > + { 0x54019, 0x84 }, > + { 0x5401a, 0x33 }, > + { 0x5401b, 0x4866 }, > + { 0x5401c, 0x4800 }, > + { 0x5401e, 0x16 }, > + { 0x5401f, 0x84 }, > + { 0x54020, 0x33 }, > + { 0x54021, 0x4866 }, > + { 0x54022, 0x4800 }, > + { 0x54024, 0x16 }, > + { 0x5402b, 0x1000 }, > + { 0x5402c, 0x1 }, > + { 0x54032, 0x8400 }, > + { 0x54033, 0x3300 }, > + { 0x54034, 0x6600 }, > + { 0x54035, 0x48 }, > + { 0x54036, 0x48 }, > + { 0x54037, 0x1600 }, > + { 0x54038, 0x8400 }, > + { 0x54039, 0x3300 }, > + { 0x5403a, 0x6600 }, > + { 0x5403b, 0x48 }, > + { 0x5403c, 0x48 }, > + { 0x5403d, 0x1600 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* P2 message block paremeter for training firmware */ > +static struct dram_cfg_param ddr_fsp2_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54002, 0x102 }, > + { 0x54003, 0x64 }, > + { 0x54004, 0x2 }, > + { 0x54005, 0x2228 }, > + { 0x54006, 0x14 }, > + { 0x54008, 0x121f }, > + { 0x54009, 0xc8 }, > + { 0x5400b, 0x2 }, > + { 0x5400f, 0x100 }, > + { 0x54012, 0x110 }, > + { 0x54019, 0x84 }, > + { 0x5401a, 0x33 }, > + { 0x5401b, 0x4866 }, > + { 0x5401c, 0x4800 }, > + { 0x5401e, 0x16 }, > + { 0x5401f, 0x84 }, > + { 0x54020, 0x33 }, > + { 0x54021, 0x4866 }, > + { 0x54022, 0x4800 }, > + { 0x54024, 0x16 }, > + { 0x5402b, 0x1000 }, > + { 0x5402c, 0x1 }, > + { 0x54032, 0x8400 }, > + { 0x54033, 0x3300 }, > + { 0x54034, 0x6600 }, > + { 0x54035, 0x48 }, > + { 0x54036, 0x48 }, > + { 0x54037, 0x1600 }, > + { 0x54038, 0x8400 }, > + { 0x54039, 0x3300 }, > + { 0x5403a, 0x6600 }, > + { 0x5403b, 0x48 }, > + { 0x5403c, 0x48 }, > + { 0x5403d, 0x1600 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* P0 2D message block paremeter for training firmware */ > +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54003, 0xbb8 }, > + { 0x54004, 0x2 }, > + { 0x54005, 0x2228 }, > + { 0x54006, 0x14 }, > + { 0x54008, 0x61 }, > + { 0x54009, 0xc8 }, > + { 0x5400b, 0x2 }, > + { 0x5400f, 0x100 }, > + { 0x54010, 0x1f7f }, > + { 0x54012, 0x110 }, > + { 0x54019, 0x2dd4 }, > + { 0x5401a, 0x33 }, > + { 0x5401b, 0x4866 }, > + { 0x5401c, 0x4800 }, > + { 0x5401e, 0x16 }, > + { 0x5401f, 0x2dd4 }, > + { 0x54020, 0x33 }, > + { 0x54021, 0x4866 }, > + { 0x54022, 0x4800 }, > + { 0x54024, 0x16 }, > + { 0x5402b, 0x1000 }, > + { 0x5402c, 0x1 }, > + { 0x54032, 0xd400 }, > + { 0x54033, 0x332d }, > + { 0x54034, 0x6600 }, > + { 0x54035, 0x48 }, > + { 0x54036, 0x48 }, > + { 0x54037, 0x1600 }, > + { 0x54038, 0xd400 }, > + { 0x54039, 0x332d }, > + { 0x5403a, 0x6600 }, > + { 0x5403b, 0x48 }, > + { 0x5403c, 0x48 }, > + { 0x5403d, 0x1600 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* DRAM PHY init engine image */ > +static struct dram_cfg_param ddr_phy_pie[] = { > + { 0xd0000, 0x0 }, > + { 0x90000, 0x10 }, > + { 0x90001, 0x400 }, > + { 0x90002, 0x10e }, > + { 0x90003, 0x0 }, > + { 0x90004, 0x0 }, > + { 0x90005, 0x8 }, > + { 0x90029, 0xb }, > + { 0x9002a, 0x480 }, > + { 0x9002b, 0x109 }, > + { 0x9002c, 0x8 }, > + { 0x9002d, 0x448 }, > + { 0x9002e, 0x139 }, > + { 0x9002f, 0x8 }, > + { 0x90030, 0x478 }, > + { 0x90031, 0x109 }, > + { 0x90032, 0x0 }, > + { 0x90033, 0xe8 }, > + { 0x90034, 0x109 }, > + { 0x90035, 0x2 }, > + { 0x90036, 0x10 }, > + { 0x90037, 0x139 }, > + { 0x90038, 0xb }, > + { 0x90039, 0x7c0 }, > + { 0x9003a, 0x139 }, > + { 0x9003b, 0x44 }, > + { 0x9003c, 0x633 }, > + { 0x9003d, 0x159 }, > + { 0x9003e, 0x14f }, > + { 0x9003f, 0x630 }, > + { 0x90040, 0x159 }, > + { 0x90041, 0x47 }, > + { 0x90042, 0x633 }, > + { 0x90043, 0x149 }, > + { 0x90044, 0x4f }, > + { 0x90045, 0x633 }, > + { 0x90046, 0x179 }, > + { 0x90047, 0x8 }, > + { 0x90048, 0xe0 }, > + { 0x90049, 0x109 }, > + { 0x9004a, 0x0 }, > + { 0x9004b, 0x7c8 }, > + { 0x9004c, 0x109 }, > + { 0x9004d, 0x0 }, > + { 0x9004e, 0x1 }, > + { 0x9004f, 0x8 }, > + { 0x90050, 0x0 }, > + { 0x90051, 0x45a }, > + { 0x90052, 0x9 }, > + { 0x90053, 0x0 }, > + { 0x90054, 0x448 }, > + { 0x90055, 0x109 }, > + { 0x90056, 0x40 }, > + { 0x90057, 0x633 }, > + { 0x90058, 0x179 }, > + { 0x90059, 0x1 }, > + { 0x9005a, 0x618 }, > + { 0x9005b, 0x109 }, > + { 0x9005c, 0x40c0 }, > + { 0x9005d, 0x633 }, > + { 0x9005e, 0x149 }, > + { 0x9005f, 0x8 }, > + { 0x90060, 0x4 }, > + { 0x90061, 0x48 }, > + { 0x90062, 0x4040 }, > + { 0x90063, 0x633 }, > + { 0x90064, 0x149 }, > + { 0x90065, 0x0 }, > + { 0x90066, 0x4 }, > + { 0x90067, 0x48 }, > + { 0x90068, 0x40 }, > + { 0x90069, 0x633 }, > + { 0x9006a, 0x149 }, > + { 0x9006b, 0x10 }, > + { 0x9006c, 0x4 }, > + { 0x9006d, 0x18 }, > + { 0x9006e, 0x0 }, > + { 0x9006f, 0x4 }, > + { 0x90070, 0x78 }, > + { 0x90071, 0x549 }, > + { 0x90072, 0x633 }, > + { 0x90073, 0x159 }, > + { 0x90074, 0xd49 }, > + { 0x90075, 0x633 }, > + { 0x90076, 0x159 }, > + { 0x90077, 0x94a }, > + { 0x90078, 0x633 }, > + { 0x90079, 0x159 }, > + { 0x9007a, 0x441 }, > + { 0x9007b, 0x633 }, > + { 0x9007c, 0x149 }, > + { 0x9007d, 0x42 }, > + { 0x9007e, 0x633 }, > + { 0x9007f, 0x149 }, > + { 0x90080, 0x1 }, > + { 0x90081, 0x633 }, > + { 0x90082, 0x149 }, > + { 0x90083, 0x0 }, > + { 0x90084, 0xe0 }, > + { 0x90085, 0x109 }, > + { 0x90086, 0xa }, > + { 0x90087, 0x10 }, > + { 0x90088, 0x109 }, > + { 0x90089, 0x9 }, > + { 0x9008a, 0x3c0 }, > + { 0x9008b, 0x149 }, > + { 0x9008c, 0x9 }, > + { 0x9008d, 0x3c0 }, > + { 0x9008e, 0x159 }, > + { 0x9008f, 0x18 }, > + { 0x90090, 0x10 }, > + { 0x90091, 0x109 }, > + { 0x90092, 0x0 }, > + { 0x90093, 0x3c0 }, > + { 0x90094, 0x109 }, > + { 0x90095, 0x18 }, > + { 0x90096, 0x4 }, > + { 0x90097, 0x48 }, > + { 0x90098, 0x18 }, > + { 0x90099, 0x4 }, > + { 0x9009a, 0x58 }, > + { 0x9009b, 0xb }, > + { 0x9009c, 0x10 }, > + { 0x9009d, 0x109 }, > + { 0x9009e, 0x1 }, > + { 0x9009f, 0x10 }, > + { 0x900a0, 0x109 }, > + { 0x900a1, 0x5 }, > + { 0x900a2, 0x7c0 }, > + { 0x900a3, 0x109 }, > + { 0x40000, 0x811 }, > + { 0x40020, 0x880 }, > + { 0x40040, 0x0 }, > + { 0x40060, 0x0 }, > + { 0x40001, 0x4008 }, > + { 0x40021, 0x83 }, > + { 0x40041, 0x4f }, > + { 0x40061, 0x0 }, > + { 0x40002, 0x4040 }, > + { 0x40022, 0x83 }, > + { 0x40042, 0x51 }, > + { 0x40062, 0x0 }, > + { 0x40003, 0x811 }, > + { 0x40023, 0x880 }, > + { 0x40043, 0x0 }, > + { 0x40063, 0x0 }, > + { 0x40004, 0x720 }, > + { 0x40024, 0xf }, > + { 0x40044, 0x1740 }, > + { 0x40064, 0x0 }, > + { 0x40005, 0x16 }, > + { 0x40025, 0x83 }, > + { 0x40045, 0x4b }, > + { 0x40065, 0x0 }, > + { 0x40006, 0x716 }, > + { 0x40026, 0xf }, > + { 0x40046, 0x2001 }, > + { 0x40066, 0x0 }, > + { 0x40007, 0x716 }, > + { 0x40027, 0xf }, > + { 0x40047, 0x2800 }, > + { 0x40067, 0x0 }, > + { 0x40008, 0x716 }, > + { 0x40028, 0xf }, > + { 0x40048, 0xf00 }, > + { 0x40068, 0x0 }, > + { 0x40009, 0x720 }, > + { 0x40029, 0xf }, > + { 0x40049, 0x1400 }, > + { 0x40069, 0x0 }, > + { 0x4000a, 0xe08 }, > + { 0x4002a, 0xc15 }, > + { 0x4004a, 0x0 }, > + { 0x4006a, 0x0 }, > + { 0x4000b, 0x625 }, > + { 0x4002b, 0x15 }, > + { 0x4004b, 0x0 }, > + { 0x4006b, 0x0 }, > + { 0x4000c, 0x4028 }, > + { 0x4002c, 0x80 }, > + { 0x4004c, 0x0 }, > + { 0x4006c, 0x0 }, > + { 0x4000d, 0xe08 }, > + { 0x4002d, 0xc1a }, > + { 0x4004d, 0x0 }, > + { 0x4006d, 0x0 }, > + { 0x4000e, 0x625 }, > + { 0x4002e, 0x1a }, > + { 0x4004e, 0x0 }, > + { 0x4006e, 0x0 }, > + { 0x4000f, 0x4040 }, > + { 0x4002f, 0x80 }, > + { 0x4004f, 0x0 }, > + { 0x4006f, 0x0 }, > + { 0x40010, 0x2604 }, > + { 0x40030, 0x15 }, > + { 0x40050, 0x0 }, > + { 0x40070, 0x0 }, > + { 0x40011, 0x708 }, > + { 0x40031, 0x5 }, > + { 0x40051, 0x0 }, > + { 0x40071, 0x2002 }, > + { 0x40012, 0x8 }, > + { 0x40032, 0x80 }, > + { 0x40052, 0x0 }, > + { 0x40072, 0x0 }, > + { 0x40013, 0x2604 }, > + { 0x40033, 0x1a }, > + { 0x40053, 0x0 }, > + { 0x40073, 0x0 }, > + { 0x40014, 0x708 }, > + { 0x40034, 0xa }, > + { 0x40054, 0x0 }, > + { 0x40074, 0x2002 }, > + { 0x40015, 0x4040 }, > + { 0x40035, 0x80 }, > + { 0x40055, 0x0 }, > + { 0x40075, 0x0 }, > + { 0x40016, 0x60a }, > + { 0x40036, 0x15 }, > + { 0x40056, 0x1200 }, > + { 0x40076, 0x0 }, > + { 0x40017, 0x61a }, > + { 0x40037, 0x15 }, > + { 0x40057, 0x1300 }, > + { 0x40077, 0x0 }, > + { 0x40018, 0x60a }, > + { 0x40038, 0x1a }, > + { 0x40058, 0x1200 }, > + { 0x40078, 0x0 }, > + { 0x40019, 0x642 }, > + { 0x40039, 0x1a }, > + { 0x40059, 0x1300 }, > + { 0x40079, 0x0 }, > + { 0x4001a, 0x4808 }, > + { 0x4003a, 0x880 }, > + { 0x4005a, 0x0 }, > + { 0x4007a, 0x0 }, > + { 0x900a4, 0x0 }, > + { 0x900a5, 0x790 }, > + { 0x900a6, 0x11a }, > + { 0x900a7, 0x8 }, > + { 0x900a8, 0x7aa }, > + { 0x900a9, 0x2a }, > + { 0x900aa, 0x10 }, > + { 0x900ab, 0x7b2 }, > + { 0x900ac, 0x2a }, > + { 0x900ad, 0x0 }, > + { 0x900ae, 0x7c8 }, > + { 0x900af, 0x109 }, > + { 0x900b0, 0x10 }, > + { 0x900b1, 0x10 }, > + { 0x900b2, 0x109 }, > + { 0x900b3, 0x10 }, > + { 0x900b4, 0x2a8 }, > + { 0x900b5, 0x129 }, > + { 0x900b6, 0x8 }, > + { 0x900b7, 0x370 }, > + { 0x900b8, 0x129 }, > + { 0x900b9, 0xa }, > + { 0x900ba, 0x3c8 }, > + { 0x900bb, 0x1a9 }, > + { 0x900bc, 0xc }, > + { 0x900bd, 0x408 }, > + { 0x900be, 0x199 }, > + { 0x900bf, 0x14 }, > + { 0x900c0, 0x790 }, > + { 0x900c1, 0x11a }, > + { 0x900c2, 0x8 }, > + { 0x900c3, 0x4 }, > + { 0x900c4, 0x18 }, > + { 0x900c5, 0xe }, > + { 0x900c6, 0x408 }, > + { 0x900c7, 0x199 }, > + { 0x900c8, 0x8 }, > + { 0x900c9, 0x8568 }, > + { 0x900ca, 0x108 }, > + { 0x900cb, 0x18 }, > + { 0x900cc, 0x790 }, > + { 0x900cd, 0x16a }, > + { 0x900ce, 0x8 }, > + { 0x900cf, 0x1d8 }, > + { 0x900d0, 0x169 }, > + { 0x900d1, 0x10 }, > + { 0x900d2, 0x8558 }, > + { 0x900d3, 0x168 }, > + { 0x900d4, 0x70 }, > + { 0x900d5, 0x788 }, > + { 0x900d6, 0x16a }, > + { 0x900d7, 0x1ff8 }, > + { 0x900d8, 0x85a8 }, > + { 0x900d9, 0x1e8 }, > + { 0x900da, 0x50 }, > + { 0x900db, 0x798 }, > + { 0x900dc, 0x16a }, > + { 0x900dd, 0x60 }, > + { 0x900de, 0x7a0 }, > + { 0x900df, 0x16a }, > + { 0x900e0, 0x8 }, > + { 0x900e1, 0x8310 }, > + { 0x900e2, 0x168 }, > + { 0x900e3, 0x8 }, > + { 0x900e4, 0xa310 }, > + { 0x900e5, 0x168 }, > + { 0x900e6, 0xa }, > + { 0x900e7, 0x408 }, > + { 0x900e8, 0x169 }, > + { 0x900e9, 0x6e }, > + { 0x900ea, 0x0 }, > + { 0x900eb, 0x68 }, > + { 0x900ec, 0x0 }, > + { 0x900ed, 0x408 }, > + { 0x900ee, 0x169 }, > + { 0x900ef, 0x0 }, > + { 0x900f0, 0x8310 }, > + { 0x900f1, 0x168 }, > + { 0x900f2, 0x0 }, > + { 0x900f3, 0xa310 }, > + { 0x900f4, 0x168 }, > + { 0x900f5, 0x1ff8 }, > + { 0x900f6, 0x85a8 }, > + { 0x900f7, 0x1e8 }, > + { 0x900f8, 0x68 }, > + { 0x900f9, 0x798 }, > + { 0x900fa, 0x16a }, > + { 0x900fb, 0x78 }, > + { 0x900fc, 0x7a0 }, > + { 0x900fd, 0x16a }, > + { 0x900fe, 0x68 }, > + { 0x900ff, 0x790 }, > + { 0x90100, 0x16a }, > + { 0x90101, 0x8 }, > + { 0x90102, 0x8b10 }, > + { 0x90103, 0x168 }, > + { 0x90104, 0x8 }, > + { 0x90105, 0xab10 }, > + { 0x90106, 0x168 }, > + { 0x90107, 0xa }, > + { 0x90108, 0x408 }, > + { 0x90109, 0x169 }, > + { 0x9010a, 0x58 }, > + { 0x9010b, 0x0 }, > + { 0x9010c, 0x68 }, > + { 0x9010d, 0x0 }, > + { 0x9010e, 0x408 }, > + { 0x9010f, 0x169 }, > + { 0x90110, 0x0 }, > + { 0x90111, 0x8b10 }, > + { 0x90112, 0x168 }, > + { 0x90113, 0x1 }, > + { 0x90114, 0xab10 }, > + { 0x90115, 0x168 }, > + { 0x90116, 0x0 }, > + { 0x90117, 0x1d8 }, > + { 0x90118, 0x169 }, > + { 0x90119, 0x80 }, > + { 0x9011a, 0x790 }, > + { 0x9011b, 0x16a }, > + { 0x9011c, 0x18 }, > + { 0x9011d, 0x7aa }, > + { 0x9011e, 0x6a }, > + { 0x9011f, 0xa }, > + { 0x90120, 0x0 }, > + { 0x90121, 0x1e9 }, > + { 0x90122, 0x8 }, > + { 0x90123, 0x8080 }, > + { 0x90124, 0x108 }, > + { 0x90125, 0xf }, > + { 0x90126, 0x408 }, > + { 0x90127, 0x169 }, > + { 0x90128, 0xc }, > + { 0x90129, 0x0 }, > + { 0x9012a, 0x68 }, > + { 0x9012b, 0x9 }, > + { 0x9012c, 0x0 }, > + { 0x9012d, 0x1a9 }, > + { 0x9012e, 0x0 }, > + { 0x9012f, 0x408 }, > + { 0x90130, 0x169 }, > + { 0x90131, 0x0 }, > + { 0x90132, 0x8080 }, > + { 0x90133, 0x108 }, > + { 0x90134, 0x8 }, > + { 0x90135, 0x7aa }, > + { 0x90136, 0x6a }, > + { 0x90137, 0x0 }, > + { 0x90138, 0x8568 }, > + { 0x90139, 0x108 }, > + { 0x9013a, 0xb7 }, > + { 0x9013b, 0x790 }, > + { 0x9013c, 0x16a }, > + { 0x9013d, 0x1f }, > + { 0x9013e, 0x0 }, > + { 0x9013f, 0x68 }, > + { 0x90140, 0x8 }, > + { 0x90141, 0x8558 }, > + { 0x90142, 0x168 }, > + { 0x90143, 0xf }, > + { 0x90144, 0x408 }, > + { 0x90145, 0x169 }, > + { 0x90146, 0xd }, > + { 0x90147, 0x0 }, > + { 0x90148, 0x68 }, > + { 0x90149, 0x0 }, > + { 0x9014a, 0x408 }, > + { 0x9014b, 0x169 }, > + { 0x9014c, 0x0 }, > + { 0x9014d, 0x8558 }, > + { 0x9014e, 0x168 }, > + { 0x9014f, 0x8 }, > + { 0x90150, 0x3c8 }, > + { 0x90151, 0x1a9 }, > + { 0x90152, 0x3 }, > + { 0x90153, 0x370 }, > + { 0x90154, 0x129 }, > + { 0x90155, 0x20 }, > + { 0x90156, 0x2aa }, > + { 0x90157, 0x9 }, > + { 0x90158, 0x8 }, > + { 0x90159, 0xe8 }, > + { 0x9015a, 0x109 }, > + { 0x9015b, 0x0 }, > + { 0x9015c, 0x8140 }, > + { 0x9015d, 0x10c }, > + { 0x9015e, 0x10 }, > + { 0x9015f, 0x8138 }, > + { 0x90160, 0x104 }, > + { 0x90161, 0x8 }, > + { 0x90162, 0x448 }, > + { 0x90163, 0x109 }, > + { 0x90164, 0xf }, > + { 0x90165, 0x7c0 }, > + { 0x90166, 0x109 }, > + { 0x90167, 0x0 }, > + { 0x90168, 0xe8 }, > + { 0x90169, 0x109 }, > + { 0x9016a, 0x47 }, > + { 0x9016b, 0x630 }, > + { 0x9016c, 0x109 }, > + { 0x9016d, 0x8 }, > + { 0x9016e, 0x618 }, > + { 0x9016f, 0x109 }, > + { 0x90170, 0x8 }, > + { 0x90171, 0xe0 }, > + { 0x90172, 0x109 }, > + { 0x90173, 0x0 }, > + { 0x90174, 0x7c8 }, > + { 0x90175, 0x109 }, > + { 0x90176, 0x8 }, > + { 0x90177, 0x8140 }, > + { 0x90178, 0x10c }, > + { 0x90179, 0x0 }, > + { 0x9017a, 0x478 }, > + { 0x9017b, 0x109 }, > + { 0x9017c, 0x0 }, > + { 0x9017d, 0x1 }, > + { 0x9017e, 0x8 }, > + { 0x9017f, 0x8 }, > + { 0x90180, 0x4 }, > + { 0x90181, 0x0 }, > + { 0x90006, 0x8 }, > + { 0x90007, 0x7c8 }, > + { 0x90008, 0x109 }, > + { 0x90009, 0x0 }, > + { 0x9000a, 0x400 }, > + { 0x9000b, 0x106 }, > + { 0xd00e7, 0x400 }, > + { 0x90017, 0x0 }, > + { 0x9001f, 0x29 }, > + { 0x90026, 0x68 }, > + { 0x400d0, 0x0 }, > + { 0x400d1, 0x101 }, > + { 0x400d2, 0x105 }, > + { 0x400d3, 0x107 }, > + { 0x400d4, 0x10f }, > + { 0x400d5, 0x202 }, > + { 0x400d6, 0x20a }, > + { 0x400d7, 0x20b }, > + { 0x2003a, 0x2 }, > + { 0x200be, 0x3 }, > + { 0x2000b, 0x34b }, > + { 0x2000c, 0xbb }, > + { 0x2000d, 0x753 }, > + { 0x2000e, 0x2c }, > + { 0x12000b, 0x70 }, > + { 0x12000c, 0x19 }, > + { 0x12000d, 0xfa }, > + { 0x12000e, 0x10 }, > + { 0x22000b, 0x1c }, > + { 0x22000c, 0x6 }, > + { 0x22000d, 0x3e }, > + { 0x22000e, 0x10 }, > + { 0x9000c, 0x0 }, > + { 0x9000d, 0x173 }, > + { 0x9000e, 0x60 }, > + { 0x9000f, 0x6110 }, > + { 0x90010, 0x2152 }, > + { 0x90011, 0xdfbd }, > + { 0x90012, 0x2060 }, > + { 0x90013, 0x6152 }, > + { 0x20010, 0x5a }, > + { 0x20011, 0x3 }, > + { 0x40080, 0xe0 }, > + { 0x40081, 0x12 }, > + { 0x40082, 0xe0 }, > + { 0x40083, 0x12 }, > + { 0x40084, 0xe0 }, > + { 0x40085, 0x12 }, > + { 0x140080, 0xe0 }, > + { 0x140081, 0x12 }, > + { 0x140082, 0xe0 }, > + { 0x140083, 0x12 }, > + { 0x140084, 0xe0 }, > + { 0x140085, 0x12 }, > + { 0x240080, 0xe0 }, > + { 0x240081, 0x12 }, > + { 0x240082, 0xe0 }, > + { 0x240083, 0x12 }, > + { 0x240084, 0xe0 }, > + { 0x240085, 0x12 }, > + { 0x400fd, 0xf }, > + { 0x10011, 0x1 }, > + { 0x10012, 0x1 }, > + { 0x10013, 0x180 }, > + { 0x10018, 0x1 }, > + { 0x10002, 0x6209 }, > + { 0x100b2, 0x1 }, > + { 0x101b4, 0x1 }, > + { 0x102b4, 0x1 }, > + { 0x103b4, 0x1 }, > + { 0x104b4, 0x1 }, > + { 0x105b4, 0x1 }, > + { 0x106b4, 0x1 }, > + { 0x107b4, 0x1 }, > + { 0x108b4, 0x1 }, > + { 0x11011, 0x1 }, > + { 0x11012, 0x1 }, > + { 0x11013, 0x180 }, > + { 0x11018, 0x1 }, > + { 0x11002, 0x6209 }, > + { 0x110b2, 0x1 }, > + { 0x111b4, 0x1 }, > + { 0x112b4, 0x1 }, > + { 0x113b4, 0x1 }, > + { 0x114b4, 0x1 }, > + { 0x115b4, 0x1 }, > + { 0x116b4, 0x1 }, > + { 0x117b4, 0x1 }, > + { 0x118b4, 0x1 }, > + { 0x12011, 0x1 }, > + { 0x12012, 0x1 }, > + { 0x12013, 0x180 }, > + { 0x12018, 0x1 }, > + { 0x12002, 0x6209 }, > + { 0x120b2, 0x1 }, > + { 0x121b4, 0x1 }, > + { 0x122b4, 0x1 }, > + { 0x123b4, 0x1 }, > + { 0x124b4, 0x1 }, > + { 0x125b4, 0x1 }, > + { 0x126b4, 0x1 }, > + { 0x127b4, 0x1 }, > + { 0x128b4, 0x1 }, > + { 0x13011, 0x1 }, > + { 0x13012, 0x1 }, > + { 0x13013, 0x180 }, > + { 0x13018, 0x1 }, > + { 0x13002, 0x6209 }, > + { 0x130b2, 0x1 }, > + { 0x131b4, 0x1 }, > + { 0x132b4, 0x1 }, > + { 0x133b4, 0x1 }, > + { 0x134b4, 0x1 }, > + { 0x135b4, 0x1 }, > + { 0x136b4, 0x1 }, > + { 0x137b4, 0x1 }, > + { 0x138b4, 0x1 }, > + { 0x20089, 0x1 }, > + { 0x20088, 0x19 }, > + { 0xc0080, 0x2 }, > + { 0xd0000, 0x1 } > +}; > + > +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { > + { > + /* P0 3000mts 1D */ > + .drate = 3000, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = ddr_fsp0_cfg, > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), > + }, > + { > + /* P1 400mts 1D */ > + .drate = 400, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = ddr_fsp1_cfg, > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), > + }, > + { > + /* P2 100mts 1D */ > + .drate = 100, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = ddr_fsp2_cfg, > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), > + }, > + { > + /* P0 3000mts 2D */ > + .drate = 3000, > + .fw_type = FW_2D_IMAGE, > + .fsp_cfg = ddr_fsp0_2d_cfg, > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), > + }, > +}; > + > +/* ddr timing config params */ > +struct dram_timing_info dram_timing = { > + .ddrc_cfg = ddr_ddrc_cfg, > + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), > + .ddrphy_cfg = ddr_ddrphy_cfg, > + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), > + .fsp_msg = ddr_dram_fsp_msg, > + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), > + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, > + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), > + .ddrphy_pie = ddr_phy_pie, > + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), > + .fsp_table = { 3000, 400, 100, }, > +}; > diff --git a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c > new file mode 100644 > index 0000000000..3913c4f242 > --- /dev/null > +++ b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c > @@ -0,0 +1,60 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Based on vendor support provided by AVNET Embedded > + * > + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH > + * Copyright 2021 General Electric Company > + * Copyright 2021 Collabora Ltd. > + */ > + > +#include <common.h> > +#include <errno.h> > +#include <miiphy.h> > +#include <netdev.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/imx8mp_pins.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/mach-imx/gpio.h> > +#include <asm/mach-imx/iomux-v3.h> > +#include <asm-generic/gpio.h> > +#include <linux/delay.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static void setup_fec(void) > +{ > + struct iomuxc_gpr_base_regs *gpr = > + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; > + > + /* Enable RGMII TX clk output */ > + setbits_le32(&gpr->gpr[1], BIT(22)); > +} > + > +static int setup_eqos(void) > +{ > + struct iomuxc_gpr_base_regs *gpr = > + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; > + > + /* set INTF as RGMII, enable RGMII TXC clock */ > + clrsetbits_le32(&gpr->gpr[1], > + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); > + setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); > + > + return set_clk_eqos(ENET_125MHZ); > +} > + > +int board_phy_config(struct phy_device *phydev) > +{ > + if (phydev->drv->config) > + phydev->drv->config(phydev); > + return 0; > +} > + > +int board_init(void) > +{ > + setup_fec(); > + > + setup_eqos(); > + > + return 0; > +} > diff --git a/board/msc/sm2s_imx8mp/spl.c b/board/msc/sm2s_imx8mp/spl.c > new file mode 100644 > index 0000000000..d20c9c52c9 > --- /dev/null > +++ b/board/msc/sm2s_imx8mp/spl.c > @@ -0,0 +1,273 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Based on vendor support provided by AVNET Embedded > + * > + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH > + * Copyright 2021 General Electric Company > + * Copyright 2021 Collabora Ltd. > + */ > + > +#include <common.h> > +#include <cpu_func.h> > +#include <fsl_esdhc_imx.h> > +#include <hang.h> > +#include <i2c.h> > +#include <image.h> > +#include <init.h> > +#include <log.h> > +#include <mmc.h> > +#include <spl.h> > +#include <asm/global_data.h> > +#include <asm/io.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/ddr.h> > +#include <asm/arch/imx8mp_pins.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/mach-imx/boot_mode.h> > +#include <asm/mach-imx/gpio.h> > +#include <asm/mach-imx/iomux-v3.h> > +#include <asm/mach-imx/mxc_i2c.h> > +#include <dm/uclass.h> > +#include <dm/device.h> > +#include <linux/delay.h> > +#include <power/pmic.h> > +#include <power/rn5t567_pmic.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int spl_board_boot_device(enum boot_device boot_dev_spl) > +{ > + return BOOT_DEVICE_BOOTROM; > +} > + > +void spl_dram_init(void) > +{ > + ddr_init(&dram_timing); > +} > + > +void spl_board_init(void) > +{ > + /* > + * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does > + * not allow to change it. Should set the clock after PMIC > + * setting done. Default is 400Mhz (system_pll1_800m with div = 2) > + * set by ROM for ND VDD_SOC > + */ > + clock_enable(CCGR_GIC, 0); > + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); > + clock_enable(CCGR_GIC, 1); > + > + puts("Normal Boot\n"); > +} > + > +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE \ > + | PAD_CTL_PE | PAD_CTL_FSEL2) > +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) > +#define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS \ > + | PAD_CTL_DSE4) > + > +static const iomux_v3_cfg_t usdhc2_pads[] = { > + MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), > + MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), > + MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), > +}; > + > +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) > +#define USDHC2_RESET_GPIO IMX_GPIO_NR(2, 19) > + > +static const iomux_v3_cfg_t usdhc3_pads[] = { > + MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + > +}; > + > +static struct fsl_esdhc_cfg usdhc_cfg[] = { > + { USDHC2_BASE_ADDR, 0, 4 }, > + { USDHC3_BASE_ADDR, 0, 8 }, > +}; > + > +int board_mmc_init(struct bd_info *bis) > +{ > + int i, ret; > + /* > + * According to the board_mmc_init() the following map is done: > + * (U-Boot device node) (Physical Port) > + * mmc0 (sd) USDHC2 > + * mmc1 (emmc) USDHC3 > + */ > + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { > + switch (i) { > + case 0: > + init_clk_usdhc(1); > + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); > + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, > + ARRAY_SIZE(usdhc2_pads)); > + gpio_request(USDHC2_RESET_GPIO, "usdhc2_reset"); > + gpio_direction_output(USDHC2_RESET_GPIO, 0); > + udelay(500); > + gpio_direction_output(USDHC2_RESET_GPIO, 1); > + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); > + gpio_direction_input(USDHC2_CD_GPIO); > + break; > + case 1: > + init_clk_usdhc(2); > + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); > + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, > + ARRAY_SIZE(usdhc3_pads)); > + break; > + default: > + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", > + i + 1); > + return -EINVAL; > + } > + > + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); > + if (ret) > + return ret; > + } > + > + return 0; > +} > + > +int board_mmc_getcd(struct mmc *mmc) > +{ > + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; > + int ret = 0; > + > + switch (cfg->esdhc_base) { > + case USDHC2_BASE_ADDR: > + ret = !gpio_get_value(USDHC2_CD_GPIO); > + break; > + case USDHC3_BASE_ADDR: > + ret = 1; > + break; > + } > + > + return ret; > +} > + > +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) > + > +static const iomux_v3_cfg_t wdog_pads[] = { > + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), > +}; > + > +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) > + > +static const iomux_v3_cfg_t ser0_pads[] = { > + MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +int board_early_init_f(void) > +{ > + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; > + > + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); > + set_wdog_reset(wdog); > + > + imx_iomux_v3_setup_multiple_pads(ser0_pads, ARRAY_SIZE(ser0_pads)); > + > + return 0; > +} > + > +static const iomux_v3_cfg_t reset_out_pad[] = { > + MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 | MUX_PAD_CTRL(0x19) > +}; > + > +#define RESET_OUT_GPIO IMX_GPIO_NR(4, 27) > + > +static void pulse_reset_out(void) > +{ > + imx_iomux_v3_setup_multiple_pads(reset_out_pad, ARRAY_SIZE(reset_out_pad)); > + > + gpio_request(RESET_OUT_GPIO, "reset_out_gpio"); > + gpio_direction_output(RESET_OUT_GPIO, 0); > + udelay(10); > + gpio_direction_output(RESET_OUT_GPIO, 1); > +} > + > +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) > +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) > +struct i2c_pads_info i2c_dev_pads = { > + .scl = { > + .i2c_mode = MX8MP_PAD_SAI5_RXFS__I2C6_SCL | PC, > + .gpio_mode = MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 | PC, > + .gp = IMX_GPIO_NR(3, 19), > + }, > + .sda = { > + .i2c_mode = MX8MP_PAD_SAI5_RXC__I2C6_SDA | PC, > + .gpio_mode = MX8MP_PAD_SAI5_RXC__GPIO3_IO20 | PC, > + .gp = IMX_GPIO_NR(3, 20), > + }, > +}; > + > +int power_init_board(void) > +{ > + struct udevice *dev; > + int ret; > + > + ret = uclass_get_device_by_seq(UCLASS_PMIC, 0, &dev); > + if (ret) { > + printf("Error: Failed to get PMIC\n"); > + return ret; > + } > + > + /* set VCC_DRAM (buck2) to 1.1V */ > + pmic_reg_write(dev, RN5T567_DC2DAC, 0x28); > + > + /* set VCC_ARM (buck2) to 0.95V */ > + pmic_reg_write(dev, RN5T567_DC3DAC, 0x1C); > + > + return 0; > +} > + > +int board_fit_config_name_match(const char *name) > +{ > + return 0; > +} > + > +void board_init_f(ulong dummy) > +{ > + int ret; > + > + arch_cpu_init(); > + > + init_uart_clk(1); > + > + board_early_init_f(); > + > + pulse_reset_out(); > + > + timer_init(); > + > + ret = spl_early_init(); > + if (ret) { > + printf("Error: failed to initialize SPL!\n"); > + hang(); > + } > + > + preloader_console_init(); > + > + enable_tzc380(); > + > + power_init_board(); > + > + spl_dram_init(); > +} > diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig > new file mode 100644 > index 0000000000..82c72a642c > --- /dev/null > +++ b/configs/msc_sm2s_imx8mp_defconfig > @@ -0,0 +1,91 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_IMX8M=y > +CONFIG_SYS_TEXT_BASE=0x40200000 > +CONFIG_SYS_MALLOC_LEN=0x2000000 > +CONFIG_SPL_GPIO=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_ENV_SIZE=0x1000 > +CONFIG_DM_GPIO=y > +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-msc-sm2s" > +CONFIG_SPL_TEXT_BASE=0x920000 > +CONFIG_TARGET_MSC_SM2S_IMX8MP=y > +CONFIG_SPL_MMC=y > +CONFIG_SPL_SERIAL=y > +CONFIG_SPL_DRIVERS_MISC=y > +CONFIG_SPL=y > +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 > +CONFIG_SYS_LOAD_ADDR=0x40480000 > +CONFIG_DISTRO_DEFAULTS=y > +CONFIG_FIT=y > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 > +CONFIG_SPL_LOAD_FIT=y > +# CONFIG_USE_SPL_FIT_GENERATOR is not set > +CONFIG_OF_SYSTEM_SETUP=y > +CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb" > +CONFIG_SPL_MAX_SIZE=0x26000 > +CONFIG_SPL_BSS_MAX_SIZE=0x400 > +CONFIG_SPL_BOARD_INIT=y > +CONFIG_SPL_BOOTROM_SUPPORT=y > +CONFIG_SPL_SYS_MALLOC_SIMPLE=y > +CONFIG_SPL_I2C=y > +CONFIG_SPL_POWER=y > +CONFIG_SPL_WATCHDOG=y > +CONFIG_SYS_PROMPT="u-boot=> " > +CONFIG_SYS_MAXARGS=64 > +CONFIG_SYS_CBSIZE=2048 > +CONFIG_SYS_PBSIZE=2074 > +CONFIG_SYS_BOOTM_LEN=0x2000000 > +# CONFIG_CMD_EXPORTENV is not set > +# CONFIG_CMD_IMPORTENV is not set > +# CONFIG_CMD_CRC32 is not set > +CONFIG_CMD_CLK=y > +CONFIG_CMD_FUSE=y > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_REGULATOR=y > +CONFIG_CMD_EXT4_WRITE=y > +CONFIG_OF_CONTROL=y > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts" > +CONFIG_ENV_OVERWRITE=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y > +CONFIG_SPL_DM=y > +CONFIG_SPL_CLK_COMPOSITE_CCF=y > +CONFIG_CLK_COMPOSITE_CCF=y > +CONFIG_SPL_CLK_IMX8MP=y > +CONFIG_CLK_IMX8MP=y > +CONFIG_MXC_GPIO=y > +CONFIG_DM_I2C=y > +CONFIG_LED=y > +CONFIG_LED_GPIO=y > +CONFIG_SUPPORT_EMMC_BOOT=y > +CONFIG_MMC_IO_VOLTAGE=y > +CONFIG_MMC_UHS_SUPPORT=y > +CONFIG_MMC_HS400_ES_SUPPORT=y > +CONFIG_MMC_HS400_SUPPORT=y > +CONFIG_FSL_USDHC=y > +CONFIG_PHY_TI=y > +CONFIG_DM_ETH=y > +CONFIG_DM_ETH_PHY=y > +CONFIG_PHY_GIGE=y > +CONFIG_DWC_ETH_QOS=y > +CONFIG_DWC_ETH_QOS_IMX=y > +CONFIG_FEC_MXC=y > +CONFIG_MII=y > +CONFIG_PINCTRL=y > +CONFIG_SPL_PINCTRL=y > +CONFIG_PINCTRL_IMX8M=y > +CONFIG_DM_PMIC=y > +CONFIG_PMIC_RN5T567=y > +CONFIG_SPL_PMIC_RN5T567=y > +CONFIG_DM_REGULATOR=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_DM_REGULATOR_GPIO=y > +CONFIG_MXC_UART=y > +CONFIG_SYSRESET=y > +CONFIG_SPL_SYSRESET=y > +CONFIG_SYSRESET_PSCI=y > diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h > new file mode 100644 > index 0000000000..42be0544ee > --- /dev/null > +++ b/include/configs/msc_sm2s_imx8mp.h > @@ -0,0 +1,96 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Based on vendor support provided by AVNET Embedded > + * > + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH > + * Copyright 2021 General Electric Company > + * Copyright 2021 Collabora Ltd. > + */ > + > +#ifndef __MSC_SM2S_IMX8MP_H > +#define __MSC_SM2S_IMX8MP_H > + > +#include <linux/sizes.h> > +#include <linux/stringify.h> > +#include <asm/arch/imx-regs.h> > + > +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 > +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > + > +#ifdef CONFIG_SPL_BUILD > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ > +#define CONFIG_SPL_STACK 0x960000 > +#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 > +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 > +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ > + > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE > + > +#endif > + > +#if defined(CONFIG_CMD_NET) > +#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */ > + > +#define CONFIG_FEC_XCV_TYPE RGMII > +#define CONFIG_FEC_MXC_PHYADDR 1 > +#define FEC_QUIRK_ENET_MAC > + > +#define DWC_NET_PHYADDR 1 > + > +#define PHY_ANEG_TIMEOUT 20000 > + > +#endif > + > +#ifndef CONFIG_SPL_BUILD > +#define BOOT_TARGET_DEVICES(func) \ > + func(MMC, mmc, 1) \ > + func(MMC, mmc, 2) > + > +#include <config_distro_bootcmd.h> > +#endif > + > +/* Initial environment variables */ > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + BOOTENV \ > + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > + "image=Image\0" \ > + "console=ttymxc1,115200\0" \ > + "fdt_addr_r=0x43000000\0" \ > + "boot_fdt=try\0" \ > + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ > + "initrd_addr=0x43800000\0" \ > + "bootm_size=0x10000000\0" \ > + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ > + > +/* Link Definitions */ > + > +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 > +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 > +#define CONFIG_SYS_INIT_SP_OFFSET \ > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > + > +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ > + > +#define CONFIG_SYS_SDRAM_BASE 0x40000000 > +#define PHYS_SDRAM 0x40000000 > +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ > +#define PHYS_SDRAM_2 0xc0000000 > +#define PHYS_SDRAM_2_SIZE 0x0 > + > +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR > + > +/* Monitor Command Prompt */ > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > + > +#define CONFIG_SYS_FSL_USDHC_NUM 2 > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > + > +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 > + > +#endif
On Thu, 2022-10-20 at 17:23 +0200, Stefano Babic wrote: > On 04.10.22 13:07, Martyn Welch wrote: > > Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in > > conjunction > > with the MSC SM2-MB-EP1 Mini-ITX Carrier Board. > > Hi Stefano, Thanks for the feedback. > I see at least some issues: > > - MAINTAINERS file is missing OK, I'll add an entry. > - a lot of symbols are set in include/configs/msc_sm2s_imx8mp.h > instead > of moving to Kbuild. Running first CI, the following are reported: > > Unmigrated symbols found in include/configs/msc_sm2s_imx8mp.h: > CONFIG_ETHPRIME > CONFIG_SPL_BSS_START_ADDR > CONFIG_SPL_STACK > CONFIG_SYS_BARGSIZE > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR > CONFIG_SYS_SPL_MALLOC_SIZE I've sorted these out for the next revision. > Unmigrated symbols found in include/configs/imx7ulp_spl.h: > CONFIG_SPL_FS_LOAD_PAYLOAD_NAME > CONFIG_SPL_STACK > CONFIG_SYS_MMCSD_FS_BOOT_PARTITION > CONFIG_SYS_SPL_MALLOC_SIZE These don't appear to be related to the changes I've made. Are these preexisting issues? Martyn > > Best regards, > Stefano > > > > > Signed-off-by: Martyn Welch <martyn.welch@collabora.com> > > --- > > > > Changes in v2: > >  - Renamed FDT to closer match kernel > >  - Sync with kernel FDT > >  - Update for changes made in U-Boot > > > > Changes in v3: > >  - Use imx8mp-u-boot.dtsi > >  - Switch to use of DM PMIC support in SPL > > > > Changes in v4: > >  - Rebased to latest imx master branch > > > >  arch/arm/dts/Makefile                        |   1 + > >  arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi     |  65 + > >  arch/arm/dts/imx8mp-msc-sm2s.dts             | 820 ++++++++ > >  arch/arm/mach-imx/imx8m/Kconfig              |   8 + > >  board/msc/sm2s_imx8mp/Kconfig                |  15 + > >  board/msc/sm2s_imx8mp/Makefile               |  12 + > >  board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg |   8 + > >  board/msc/sm2s_imx8mp/lpddr4_timing.c        | 1842 > > +++++++++++++++++ > >  board/msc/sm2s_imx8mp/sm2s_imx8mp.c          |  60 + > >  board/msc/sm2s_imx8mp/spl.c                  | 273 +++ > >  configs/msc_sm2s_imx8mp_defconfig            |  91 + > >  include/configs/msc_sm2s_imx8mp.h            |  96 + > >  12 files changed, 3291 insertions(+) > >  create mode 100644 arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi > >  create mode 100644 arch/arm/dts/imx8mp-msc-sm2s.dts > >  create mode 100644 board/msc/sm2s_imx8mp/Kconfig > >  create mode 100644 board/msc/sm2s_imx8mp/Makefile > >  create mode 100644 board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg > >  create mode 100644 board/msc/sm2s_imx8mp/lpddr4_timing.c > >  create mode 100644 board/msc/sm2s_imx8mp/sm2s_imx8mp.c > >  create mode 100644 board/msc/sm2s_imx8mp/spl.c > >  create mode 100644 configs/msc_sm2s_imx8mp_defconfig > >  create mode 100644 include/configs/msc_sm2s_imx8mp.h > > > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > > index 965895bc2a..a5de6e1b5e 100644 > > --- a/arch/arm/dts/Makefile > > +++ b/arch/arm/dts/Makefile > > @@ -970,6 +970,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ > >         imx8mq-phanbell.dtb \ > >         imx8mp-dhcom-pdk2.dtb \ > >         imx8mp-evk.dtb \ > > +       imx8mp-msc-sm2s.dtb \ > >         imx8mp-phyboard-pollux-rdk.dtb \ > >         imx8mp-venice.dtb \ > >         imx8mp-venice-gw74xx.dtb \ > > diff --git a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi > > b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi > > new file mode 100644 > > index 0000000000..cf591adf5a > > --- /dev/null > > +++ b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi > > @@ -0,0 +1,65 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019 NXP > > + */ > > + > > +#include "imx8mp-u-boot.dtsi" > > + > > +/ { > > +       model = "MSC SM2S-IMX8MPLUS"; > > +       compatible = "avnet,sm2s-imx8mp", "fsl,imx8mp"; > > + > > +       wdt-reboot { > > +               compatible = "wdt-reboot"; > > +               wdt = <&wdog1>; > > +               u-boot,dm-spl; > > +       }; > > +}; > > + > > +®_usdhc2_vmmc { > > +       u-boot,dm-spl; > > +}; > > + > > +&gpio1 { > > +       u-boot,dm-spl; > > +}; > > + > > +&gpio2 { > > +       u-boot,dm-spl; > > +}; > > + > > +&gpio3 { > > +       u-boot,dm-spl; > > +}; > > + > > +&i2c1 { > > +       u-boot,dm-spl; > > +}; > > + > > +&i2c2 { > > +       u-boot,dm-spl; > > +}; > > + > > +&i2c3 { > > +       u-boot,dm-spl; > > +}; > > + > > +&i2c4 { > > +       u-boot,dm-spl; > > +}; > > + > > +&i2c5 { > > +       u-boot,dm-spl; > > +}; > > + > > +&i2c6 { > > +       u-boot,dm-spl; > > +}; > > + > > +&pinctrl_i2c6 { > > +       u-boot,dm-spl; > > +}; > > + > > +&pmic { > > +       u-boot,dm-spl; > > +}; > > diff --git a/arch/arm/dts/imx8mp-msc-sm2s.dts > > b/arch/arm/dts/imx8mp-msc-sm2s.dts > > new file mode 100644 > > index 0000000000..5dbec71747 > > --- /dev/null > > +++ b/arch/arm/dts/imx8mp-msc-sm2s.dts > > @@ -0,0 +1,820 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2022 Avnet Embedded GmbH > > + */ > > + > > +/dts-v1/; > > + > > +#include "imx8mp.dtsi" > > +#include <dt-bindings/net/ti-dp83867.h> > > + > > +/ { > > +       aliases { > > +               rtc0 = &sys_rtc; > > +               rtc1 = &snvs_rtc; > > +       }; > > + > > +       chosen { > > +               stdout-path = &uart2; > > +       }; > > + > > +       reg_usb0_host_vbus: regulator-usb0-vbus { > > +               compatible = "regulator-fixed"; > > +               regulator-name = "usb0_host_vbus"; > > +               pinctrl-names = "default"; > > +               pinctrl-0 = <&pinctrl_usb0_vbus>; > > +               regulator-min-microvolt = <5000000>; > > +               regulator-max-microvolt = <5000000>; > > +               gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; > > +               enable-active-high; > > +       }; > > + > > +       reg_usb1_host_vbus: regulator-usb1-vbus { > > +               compatible = "regulator-fixed"; > > +               regulator-name = "usb1_host_vbus"; > > +               pinctrl-names = "default"; > > +               pinctrl-0 = <&pinctrl_usb1_vbus>; > > +               regulator-min-microvolt = <5000000>; > > +               regulator-max-microvolt = <5000000>; > > +               gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; > > +               enable-active-high; > > +       }; > > + > > +       reg_usdhc2_vmmc: regulator-usdhc2 { > > +               compatible = "regulator-fixed"; > > +               pinctrl-names = "default"; > > +               pinctrl-0 = <&pinctrl_usdhc2_vmmc>; > > +               regulator-name = "VSD_3V3"; > > +               regulator-min-microvolt = <3300000>; > > +               regulator-max-microvolt = <3300000>; > > +               gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > > +               enable-active-high; > > +               startup-delay-us = <100>; > > +               off-on-delay-us = <12000>; > > +       }; > > + > > +       reg_flexcan1_xceiver: regulator-flexcan1 { > > +               compatible = "regulator-fixed"; > > +               regulator-name = "flexcan1-xceiver"; > > +               regulator-min-microvolt = <3300000>; > > +               regulator-max-microvolt = <3300000>; > > +       }; > > + > > +       reg_flexcan2_xceiver: regulator-flexcan2 { > > +               compatible = "regulator-fixed"; > > +               regulator-name = "flexcan2-xceiver"; > > +               regulator-min-microvolt = <3300000>; > > +               regulator-max-microvolt = <3300000>; > > +       }; > > + > > +       lcd0_backlight: backlight-0 { > > +               compatible = "pwm-backlight"; > > +               pinctrl-names = "default"; > > +               pinctrl-0 = <&pinctrl_lcd0_backlight>; > > +               pwms = <&pwm1 0 100000 0>; > > +               brightness-levels = <0 255>; > > +               num-interpolated-steps = <255>; > > +               default-brightness-level = <255>; > > +               enable-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; > > +               status = "disabled"; > > +       }; > > + > > +       lcd1_backlight: backlight-1 { > > +               compatible = "pwm-backlight"; > > +               pinctrl-names = "default"; > > +               pinctrl-0 = <&pinctrl_lcd1_backlight>; > > +               pwms = <&pwm2 0 100000 0>; > > +               brightness-levels = <0 255>; > > +               num-interpolated-steps = <255>; > > +               default-brightness-level = <255>; > > +               enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; > > +               status = "disabled"; > > +       }; > > + > > +       leds { > > +               compatible = "gpio-leds"; > > +               pinctrl-names = "default"; > > +               pinctrl-0 = <&pinctrl_leds>; > > +               status = "okay"; > > + > > +               led-sw { > > +                       label = "sw-led"; > > +                       gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; > > +                       default-state = "off"; > > +                       linux,default-trigger = "heartbeat"; > > +               }; > > +       }; > > + > > +       extcon_usb0: extcon-usb0 { > > +               compatible = "linux,extcon-usb-gpio"; > > +               pinctrl-names = "default"; > > +               pinctrl-0 = <&pinctrl_usb0_extcon>; > > +               id-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; > > +       }; > > +}; > > + > > +&A53_0 { > > +       cpu-supply = <&vcc_arm>; > > +}; > > + > > +&A53_1 { > > +       cpu-supply = <&vcc_arm>; > > +}; > > + > > +&A53_2 { > > +       cpu-supply = <&vcc_arm>; > > +}; > > + > > +&A53_3 { > > +       cpu-supply = <&vcc_arm>; > > +}; > > + > > +&ecspi1 { > > +       #address-cells = <1>; > > +       #size-cells = <0>; > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_ecspi1>; > > +       cs-gpios = <0>, <&gpio2 8 GPIO_ACTIVE_LOW>; > > +}; > > + > > +&ecspi2 { > > +       #address-cells = <1>; > > +       #size-cells = <0>; > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_ecspi2>; > > +       cs-gpios = <0>, <&gpio2 9 GPIO_ACTIVE_LOW>; > > +}; > > + > > +&eqos { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_eqos>; > > +       phy-mode = "rgmii-id"; > > +       phy-handle = <ðphy0>; > > +       status = "okay"; > > + > > +       mdio { > > +               compatible = "snps,dwmac-mdio"; > > +               #address-cells = <1>; > > +               #size-cells = <0>; > > + > > +               ethphy0: ethernet-phy@1 { > > +                       compatible = "ethernet-phy-ieee802.3-c22"; > > +                       reg = <1>; > > +                       eee-broken-1000t; > > +                       reset-gpios = <&tca6424 16 > > GPIO_ACTIVE_LOW>; > > +                       reset-assert-us = <1000>; > > +                       reset-deassert-us = <1000>; > > +                       ti,rx-internal-delay = > > <DP83867_RGMIIDCTL_2_25_NS>; > > +                       ti,tx-internal-delay = > > <DP83867_RGMIIDCTL_2_25_NS>; > > +                       ti,fifo-depth = > > <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > > +                       ti,clk-output-sel = > > <DP83867_CLK_O_SEL_OFF>; > > +               }; > > +       }; > > +}; > > + > > +&fec { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_fec>; > > +       phy-mode = "rgmii-id"; > > +       phy-handle = <ðphy1>; > > +       fsl,magic-packet; > > +       status = "okay"; > > + > > +       mdio { > > +               #address-cells = <1>; > > +               #size-cells = <0>; > > + > > +               ethphy1: ethernet-phy@1 { > > +                       compatible = "ethernet-phy-ieee802.3-c22"; > > +                       reg = <1>; > > +                       eee-broken-1000t; > > +                       reset-gpios = <&tca6424 17 > > GPIO_ACTIVE_LOW>; > > +                       reset-assert-us = <1000>; > > +                       reset-deassert-us = <1000>; > > +                       ti,rx-internal-delay = > > <DP83867_RGMIIDCTL_2_25_NS>; > > +                       ti,tx-internal-delay = > > <DP83867_RGMIIDCTL_2_25_NS>; > > +                       ti,fifo-depth = > > <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > > +                       ti,clk-output-sel = > > <DP83867_CLK_O_SEL_OFF>; > > +               }; > > +       }; > > +}; > > + > > +&i2c1 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_i2c1>; > > +       clock-frequency = <400000>; > > +       status = "okay"; > > + > > +       id_eeprom: eeprom@50 { > > +               compatible = "atmel,24c64"; > > +               reg = <0x50>; > > +               pagesize = <32>; > > +       }; > > +}; > > + > > +&i2c2 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_i2c2>; > > +       clock-frequency = <400000>; > > +       status = "disabled"; > > +}; > > + > > +&i2c3 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_i2c3>; > > +       clock-frequency = <400000>; > > +       status = "disabled"; > > +}; > > + > > +&i2c4 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_i2c4>; > > +       clock-frequency = <400000>; > > +       status = "disabled"; > > +}; > > + > > +&i2c5 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_i2c5>; > > +       clock-frequency = <400000>; > > +       status = "disabled"; > > +}; > > + > > +&i2c6 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_i2c6>; > > +       clock-frequency = <400000>; > > +       status = "okay"; > > + > > +       tca6424: gpio@22 { > > +               compatible = "ti,tca6424"; > > +               reg = <0x22>; > > +               pinctrl-names = "default"; > > +               pinctrl-0 = <&pinctrl_tca6424>; > > +               gpio-controller; > > +               #gpio-cells = <2>; > > +               gpio-line-names = "BOOT_SEL0#", "BOOT_SEL1#", > > "BOOT_SEL2#", > > +                       "gbe0_int", "gbe1_int", "pmic_int", > > "rtc_int", "lvds_int", > > +                       "PCIE_WAKE#", "cam2_rst", "cam2_pwr", > > "SLEEP#", > > +                       "wifi_pd", "tpm_int", "wifi_int", > > "PCIE_A_RST#", > > +                       "gbe0_rst", "gbe1_rst", "LID#", "BATLOW#", > > "CHARGING#", > > +                       "CHARGER_PRSNT#"; > > +               interrupt-parent = <&gpio1>; > > +               interrupts = <9 IRQ_TYPE_EDGE_RISING>; > > +               interrupt-controller; > > +               #interrupt-cells = <2>; > > +       }; > > + > > +       dsi_lvds_bridge: bridge@2d { > > +               compatible = "ti,sn65dsi83"; > > +               reg = <0x2d>; > > +               pinctrl-names = "default"; > > +               pinctrl-0 = <&pinctrl_lvds_bridge>; > > +               enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; > > +               status = "disabled"; > > +       }; > > + > > +       pmic: pmic@30 { > > +               compatible = "ricoh,rn5t567"; > > +               reg = <0x30>; > > +               interrupt-parent = <&tca6424>; > > +               interrupts = <5 IRQ_TYPE_EDGE_FALLING>; > > + > > +               regulators { > > +                       DCDC1 { > > +                               regulator-name = "VCC_SOC"; > > +                               regulator-always-on; > > +                               regulator-min-microvolt = <950000>; > > +                               regulator-max-microvolt = <950000>; > > +                       }; > > + > > +                       DCDC2 { > > +                               regulator-name = "VCC_DRAM"; > > +                               regulator-always-on; > > +                               regulator-min-microvolt = > > <1100000>; > > +                               regulator-max-microvolt = > > <1100000>; > > +                       }; > > + > > +                       vcc_arm: DCDC3 { > > +                               regulator-name = "VCC_ARM"; > > +                               regulator-always-on; > > +                               regulator-min-microvolt = <950000>; > > +                               regulator-max-microvolt = <950000>; > > +                       }; > > + > > +                       DCDC4 { > > +                               regulator-name = "VCC_1V8"; > > +                               regulator-always-on; > > +                               regulator-min-microvolt = > > <1800000>; > > +                               regulator-max-microvolt = > > <1800000>; > > +                       }; > > + > > +                       LDO1 { > > +                               regulator-name = "VCC_LDO1_2V5"; > > +                               regulator-always-on; > > +                               regulator-min-microvolt = > > <2500000>; > > +                               regulator-max-microvolt = > > <2500000>; > > +                       }; > > + > > +                       LDO2 { > > +                               regulator-name = "VCC_LDO2_1V8"; > > +                               regulator-always-on; > > +                               regulator-min-microvolt = > > <1800000>; > > +                               regulator-max-microvolt = > > <1800000>; > > +                       }; > > + > > +                       LDO3 { > > +                               regulator-name = "VCC_ETH_2V5"; > > +                               regulator-always-on; > > +                               regulator-min-microvolt = > > <2500000>; > > +                               regulator-max-microvolt = > > <2500000>; > > +                       }; > > + > > +                       LDO4 { > > +                               regulator-name = "VCC_DDR4_2V5"; > > +                               regulator-always-on; > > +                               regulator-min-microvolt = > > <2500000>; > > +                               regulator-max-microvolt = > > <2500000>; > > +                       }; > > + > > +                       LDO5 { > > +                               regulator-name = "VCC_LDO5_1V8"; > > +                               regulator-always-on; > > +                               regulator-min-microvolt = > > <1800000>; > > +                               regulator-max-microvolt = > > <1800000>; > > +                       }; > > + > > +                       LDORTC1 { > > +                               regulator-name = "VCC_SNVS_1V8"; > > +                               regulator-always-on; > > +                               regulator-min-microvolt = > > <1800000>; > > +                               regulator-max-microvolt = > > <1800000>; > > +                       }; > > + > > +                       LDORTC2 { > > +                               regulator-name = "VCC_SNVS_3V3"; > > +                               regulator-always-on; > > +                               regulator-min-microvolt = > > <3300000>; > > +                               regulator-max-microvolt = > > <3300000>; > > +                       }; > > +               }; > > +       }; > > + > > +       sys_rtc: rtc@32 { > > +               compatible = "ricoh,r2221tl"; > > +               reg = <0x32>; > > +               interrupt-parent = <&tca6424>; > > +               interrupts = <6 IRQ_TYPE_EDGE_FALLING>; > > +       }; > > + > > +       tmp_sensor: temperature-sensor@71 { > > +               compatible = "ti,tmp103"; > > +               reg = <0x71>; > > +       }; > > +}; > > + > > +&flexcan1 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_flexcan1>; > > +       xceiver-supply = <®_flexcan1_xceiver>; > > +       status = "disabled"; > > +}; > > + > > +&flexcan2 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_flexcan2>; > > +       xceiver-supply = <®_flexcan2_xceiver>; > > +       status = "disabled"; > > +}; > > + > > +&flexspi { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_flexspi0>; > > +       status = "okay"; > > + > > +       qspi_flash: flash@0 { > > +               compatible = "jedec,spi-nor"; > > +               reg = <0>; > > +               #address-cells = <1>; > > +               #size-cells = <1>; > > +               spi-max-frequency = <80000000>; > > +               spi-tx-bus-width = <4>; > > +               spi-rx-bus-width = <4>; > > +       }; > > +}; > > + > > +&pwm1 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_pwm1>; > > +       status = "disabled"; > > +}; > > + > > +&pwm2 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_pwm2>; > > +       status = "disabled"; > > +}; > > + > > +&pwm3 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_pwm3>; > > +       status = "disabled"; > > +}; > > + > > +&pwm4 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_pwm4>; > > +       status = "disabled"; > > +}; > > + > > +&snvs_pwrkey { > > +       status = "okay"; > > +}; > > + > > +&uart1 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_uart1>; > > +       status = "okay"; > > +}; > > + > > +&uart2 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_uart2>; > > +       uart-has-rtscts; > > +       status = "okay"; > > +}; > > + > > +&uart3 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_uart3>; > > +       uart-has-rtscts; > > +       status = "okay"; > > +}; > > + > > +&uart4 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_uart4>; > > +       status = "disabled"; > > +}; > > + > > +&usb3_phy0 { > > +       vbus-supply = <®_usb0_host_vbus>; > > +       status = "okay"; > > +}; > > + > > +&usb3_phy1 { > > +       vbus-supply = <®_usb1_host_vbus>; > > +       status = "okay"; > > +}; > > + > > +&usb3_0 { > > +       status = "okay"; > > +}; > > + > > +&usb3_1 { > > +       status = "okay"; > > +}; > > + > > +&usb_dwc3_0 { > > +       dr_mode = "otg"; > > +       hnp-disable; > > +       srp-disable; > > +       adp-disable; > > +       extcon = <&extcon_usb0>; > > +       status = "okay"; > > +}; > > + > > +&usb_dwc3_1 { > > +       dr_mode = "host"; > > +       status = "okay"; > > +}; > > + > > +&usdhc2 { > > +       assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; > > +       assigned-clock-rates = <400000000>; > > +       pinctrl-names = "default", "state_100mhz", "state_200mhz"; > > +       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > > +       pinctrl-1 = <&pinctrl_usdhc2_100mhz>, > > <&pinctrl_usdhc2_gpio>; > > +       pinctrl-2 = <&pinctrl_usdhc2_200mhz>, > > <&pinctrl_usdhc2_gpio>; > > +       cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; > > +       wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; > > +       bus-width = <4>; > > +       vmmc-supply = <®_usdhc2_vmmc>; > > +       status = "okay"; > > +}; > > + > > +&usdhc3 { > > +       assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; > > +       assigned-clock-rates = <400000000>; > > +       pinctrl-names = "default", "state_100mhz", "state_200mhz"; > > +       pinctrl-0 = <&pinctrl_usdhc3>; > > +       pinctrl-1 = <&pinctrl_usdhc3_100mhz>; > > +       pinctrl-2 = <&pinctrl_usdhc3_200mhz>; > > +       bus-width = <8>; > > +       non-removable; > > +       status = "okay"; > > +}; > > + > > +&wdog1 { > > +       pinctrl-names = "default"; > > +       pinctrl-0 = <&pinctrl_wdog>; > > +       fsl,ext-reset-output; > > +       status = "okay"; > > +}; > > + > > +&iomuxc { > > +       pinctrl_ecspi1: ecspi1grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO     > >      0x82>, > > +                       <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI     > >      0x82>, > > +                       <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK     > >      0x82>, > > +                       <MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0       > >      0x40000>, > > +                       <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08        > >      0x40000>; > > +       }; > > + > > +       pinctrl_ecspi2: ecspi2grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO     > >      0x82>, > > +                       <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI     > >      0x82>, > > +                       <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK     > >      0x82>, > > +                       <MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0       > >      0x40000>, > > +                       <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09        > >      0x40000>; > > +       }; > > + > > +       pinctrl_eqos: eqosgrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC       > >      0x3>, > > +                       <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO     > >      0x3>, > > +                       <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 > >      0x91>, > > +                       <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 > >      0x91>, > > +                       <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 > >      0x91>, > > +                       <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 > >      0x91>, > > +                       <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_ > > GENERATE_RX_CLK      0x91>, > > +                       <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_R > > X_CTL        0x91>, > > +                       <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 > >      0x1f>, > > +                       <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 > >      0x1f>, > > +                       <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 > >      0x1f>, > > +                       <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 > >      0x1f>, > > +                       <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_T > > X_CTL        0x1f>, > > +                       <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_ > > GENERATE_TX_CLK      0x1f>; > > +       }; > > + > > +       pinctrl_fec: fecgrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC         > >      0x3>, > > +                       <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO        > >      0x3>, > > +                       <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0   > >      0x91>, > > +                       <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1   > >      0x91>, > > +                       <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2   > >      0x91>, > > +                       <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3   > >      0x91>, > > +                       <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC    > >      0x91>, > > +                       <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL > >      0x91>, > > +                       <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0   > >      0x1f>, > > +                       <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1   > >      0x1f>, > > +                       <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2   > >      0x1f>, > > +                       <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3   > >      0x1f>, > > +                       <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL > >      0x1f>, > > +                       <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC   > >      0x1f>; > > +       }; > > + > > +       pinctrl_flexcan1: flexcan1grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX           > >      0x154>, > > +                       <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX           > >      0x154>; > > +       }; > > + > > +       pinctrl_flexcan2: flexcan2grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX           > >      0x154>, > > +                       <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX           > >      0x154>; > > +       }; > > + > > +       pinctrl_flexspi0: flexspi0grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK     > >      0x1c2>, > > +                       <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B  > >      0x82>, > > +                       <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 > >      0x82>, > > +                       <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 > >      0x82>, > > +                       <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 > >      0x82>, > > +                       <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 > >      0x82>, > > +                       <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14         > >      0x19>; > > +       }; > > + > > +       pinctrl_i2c1: i2c1grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL           > >      0x400001c3>, > > +                       <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA           > >      0x400001c3>; > > +       }; > > + > > +       pinctrl_i2c2: i2c2grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL           > >      0x400001c3>, > > +                       <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA           > >      0x400001c3>; > > +       }; > > + > > +       pinctrl_i2c3: i2c3grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL           > >      0x400001c3>, > > +                       <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA           > >      0x400001c3>; > > +       }; > > + > > +       pinctrl_i2c4: i2c4grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL           > >      0x400001c3>, > > +                       <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA           > >      0x400001c3>; > > +       }; > > + > > +       pinctrl_i2c5: i2c5grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL           > >      0x400001c3>, > > +                       <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA           > >      0x400001c3>; > > +       }; > > + > > +       pinctrl_i2c6: i2c6grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL          > >      0x400001c3>, > > +                       <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA           > >      0x400001c3>; > > +       }; > > + > > +       pinctrl_lcd0_backlight: lcd0-backlightgrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05       > >      0x41>; > > +       }; > > + > > +       pinctrl_lcd1_backlight: lcd1-backlightgrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06       > >      0x41>; > > +       }; > > + > > +       pinctrl_leds: ledsgrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08       > >      0x19>; > > +       }; > > + > > +       pinctrl_lvds_bridge: lvds-bridgegrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07       > >      0x41>; > > +       }; > > + > > +       pinctrl_pwm1: pwm1grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT      > >      0x116>; > > +       }; > > + > > +       pinctrl_pwm2: pwm2grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT          > >      0x116>; > > +       }; > > + > > +       pinctrl_pwm3: pwm3grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT         > >      0x116>; > > +       }; > > + > > +       pinctrl_pwm4: pwm4grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT          > >      0x116>; > > +       }; > > + > > +       pinctrl_tca6424: tca6424grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09       > >      0x41>; > > +       }; > > + > > +       pinctrl_uart1: uart1grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX      > >      0x49>, > > +                       <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX      > >      0x49>; > > +       }; > > + > > +       pinctrl_uart2: uart2grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06        > >      0x1c4>, > > +                       <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07        > >      0x1c4>, > > +                       <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX      > >      0x49>, > > +                       <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX      > >      0x49>; > > +       }; > > + > > +       pinctrl_uart3: uart3grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10      > >      0x1c4>, > > +                       <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11       > >      0x1c4>, > > +                       <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX      > >      0x49>, > > +                       <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX      > >      0x49>; > > +       }; > > + > > +       pinctrl_uart4: uart4grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX      > >      0x49>, > > +                       <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX      > >      0x49>; > > +       }; > > + > > +       pinctrl_usb0_extcon: usb0-extcongrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03       > >      0x19>; > > +       }; > > + > > +       pinctrl_usb0_vbus: usb0-vbusgrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12       > >      0x19>; > > +       }; > > + > > +       pinctrl_usb1_vbus: usb1-vbusgrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14       > >      0x19>; > > +       }; > > + > > +       pinctrl_usdhc2_gpio: usdhc2-gpiogrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12         > >      0x1c4>, > > +                       <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20           > >      0x1c4>; > > +       }; > > + > > +       pinctrl_usdhc2: usdhc2grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK          > >      0x190>, > > +                       <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD          > >      0x1d0>, > > +                       <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0      > >      0x1d0>, > > +                       <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1      > >      0x1d0>, > > +                       <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2      > >      0x1d0>, > > +                       <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3      > >      0x1d0>, > > +                       <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT   > >      0xc1>; > > +       }; > > + > > +       pinctrl_usdhc2_vmmc: usdhc2-vmmcgrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19      > >      0x41>; > > +       }; > > + > > +       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK          > >      0x194>, > > +                       <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD          > >      0x1d4>, > > +                       <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0      > >      0x1d4>, > > +                       <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1      > >      0x1d4>, > > +                       <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2      > >      0x1d4>, > > +                       <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3      > >      0x1d4>, > > +                       <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT   > >      0xc1>; > > +       }; > > + > > +       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK          > >      0x196>, > > +                       <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD          > >      0x1d6>, > > +                       <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0      > >      0x1d6>, > > +                       <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1      > >      0x1d6>, > > +                       <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2      > >      0x1d6>, > > +                       <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3      > >      0x1d6>, > > +                       <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT   > >      0xc1>; > > +       }; > > + > > +       pinctrl_usdhc3: usdhc3grp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK        > >      0x190>, > > +                       <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD        > >      0x1d0>, > > +                       <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0    > >      0x1d0>, > > +                       <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1    > >      0x1d0>, > > +                       <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2    > >      0x1d0>, > > +                       <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3    > >      0x1d0>, > > +                       <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4      > >      0x1d0>, > > +                       <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5     > >      0x1d0>, > > +                       <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6     > >      0x1d0>, > > +                       <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7       > >      0x1d0>, > > +                       <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE    > >      0x190>; > > +       }; > > + > > +       pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK        > >      0x194>, > > +                       <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD        > >      0x1d4>, > > +                       <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0    > >      0x1d4>, > > +                       <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1    > >      0x1d4>, > > +                       <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2    > >      0x1d4>, > > +                       <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3    > >      0x1d4>, > > +                       <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4      > >      0x1d4>, > > +                       <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5     > >      0x1d4>, > > +                       <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6     > >      0x1d4>, > > +                       <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7       > >      0x1d4>, > > +                       <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE    > >      0x194>; > > +       }; > > + > > +       pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK        > >      0x196>, > > +                       <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD        > >      0x1d6>, > > +                       <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0    > >      0x1d6>, > > +                       <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1    > >      0x1d6>, > > +                       <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2    > >      0x1d6>, > > +                       <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3    > >      0x1d6>, > > +                       <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4      > >      0x1d6>, > > +                       <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5     > >      0x1d6>, > > +                       <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6     > >      0x1d6>, > > +                       <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7       > >      0x1d6>, > > +                       <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE    > >      0x196>; > > +       }; > > + > > +       pinctrl_wdog: wdoggrp { > > +               fsl,pins = > > +                       <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B     > >      0xc6>; > > +       }; > > +}; > > diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach- > > imx/imx8m/Kconfig > > index 3470160990..ee62b958a8 100644 > > --- a/arch/arm/mach-imx/imx8m/Kconfig > > +++ b/arch/arm/mach-imx/imx8m/Kconfig > > @@ -270,6 +270,13 @@ config TARGET_IMX8MP_RSB3720A1_6G > >         select SUPPORT_SPL > >         select IMX8M_LPDDR4 > >  > > +config TARGET_MSC_SM2S_IMX8MP > > +       bool "MSC SMARC2 i.MX8MPLUS" > > +       select BINMAN > > +       select IMX8MP > > +       select SUPPORT_SPL > > +       select IMX8M_LPDDR4 > > + > >  config TARGET_LIBREM5 > >         bool "Purism Librem5 Phone" > >         select BINMAN > > @@ -296,6 +303,7 @@ source "board/google/imx8mq_phanbell/Kconfig" > >  source "board/kontron/pitx_imx8m/Kconfig" > >  source "board/kontron/sl-mx8mm/Kconfig" > >  source "board/menlo/mx8menlo/Kconfig" > > +source "board/msc/sm2s_imx8mp/Kconfig" > >  source "board/phytec/phycore_imx8mm/Kconfig" > >  source "board/phytec/phycore_imx8mp/Kconfig" > >  source "board/purism/librem5/Kconfig" > > diff --git a/board/msc/sm2s_imx8mp/Kconfig > > b/board/msc/sm2s_imx8mp/Kconfig > > new file mode 100644 > > index 0000000000..f71a5b2bcd > > --- /dev/null > > +++ b/board/msc/sm2s_imx8mp/Kconfig > > @@ -0,0 +1,15 @@ > > +if TARGET_MSC_SM2S_IMX8MP > > + > > +config SYS_BOARD > > +       default "sm2s_imx8mp" > > + > > +config SYS_VENDOR > > +       default "msc" > > + > > +config SYS_CONFIG_NAME > > +       default "msc_sm2s_imx8mp" > > + > > +config IMX_CONFIG > > +       default "board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg" > > + > > +endif > > diff --git a/board/msc/sm2s_imx8mp/Makefile > > b/board/msc/sm2s_imx8mp/Makefile > > new file mode 100644 > > index 0000000000..f60dd7260c > > --- /dev/null > > +++ b/board/msc/sm2s_imx8mp/Makefile > > @@ -0,0 +1,12 @@ > > +# > > +# Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH > > +# > > +# SPDX-License-Identifier:     GPL-2.0 > > +# > > + > > +ifdef CONFIG_SPL_BUILD > > +obj-y += spl.o lpddr4_timing.o > > +else > > +obj-y += sm2s_imx8mp.o > > +endif > > + > > diff --git a/board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg > > b/board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg > > new file mode 100644 > > index 0000000000..8aadedb102 > > --- /dev/null > > +++ b/board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg > > @@ -0,0 +1,8 @@ > > +/* SPDX-License-Identifier: GPL-2.0+ */ > > +/* > > + * Copyright 2021 NXP > > + */ > > + > > +ROM_VERSION    v2 > > +BOOT_FROM      sd > > +LOADER         u-boot-spl-ddr.bin      0x920000 > > diff --git a/board/msc/sm2s_imx8mp/lpddr4_timing.c > > b/board/msc/sm2s_imx8mp/lpddr4_timing.c > > new file mode 100644 > > index 0000000000..e0d659af91 > > --- /dev/null > > +++ b/board/msc/sm2s_imx8mp/lpddr4_timing.c > > @@ -0,0 +1,1842 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019 NXP > > + */ > > + > > +#include <linux/kernel.h> > > +#include <asm/arch/ddr.h> > > + > > +static struct dram_cfg_param ddr_ddrc_cfg[] = { > > +       /** Initialize DDRC registers **/ > > +       { 0x3d400304, 0x1 }, > > +       { 0x3d400030, 0x1 }, > > +       { 0x3d400000, 0xa1080020 }, > > +       { 0x3d400020, 0x1223 }, > > +       { 0x3d400024, 0x16e3600 }, > > +       { 0x3d400064, 0x5b00d2 }, > > +       { 0x3d400070, 0x61027f10 }, > > +       { 0x3d400074, 0x7b0 }, > > +       { 0x3d4000d0, 0xc00305ba }, > > +       { 0x3d4000d4, 0x940000 }, > > +       { 0x3d4000dc, 0xd4002d }, > > +       { 0x3d4000e0, 0x330000 }, > > +       { 0x3d4000e8, 0x660048 }, > > +       { 0x3d4000ec, 0x160048 }, > > +       { 0x3d400100, 0x191e1920 }, > > +       { 0x3d400104, 0x60630 }, > > +       { 0x3d40010c, 0xb0b000 }, > > +       { 0x3d400110, 0xe04080e }, > > +       { 0x3d400114, 0x2040c0c }, > > +       { 0x3d400118, 0x1010007 }, > > +       { 0x3d40011c, 0x401 }, > > +       { 0x3d400130, 0x20600 }, > > +       { 0x3d400134, 0xc100002 }, > > +       { 0x3d400138, 0xd8 }, > > +       { 0x3d400144, 0x96004b }, > > +       { 0x3d400180, 0x2ee0017 }, > > +       { 0x3d400184, 0x2605b8e }, > > +       { 0x3d400188, 0x0 }, > > +       { 0x3d400190, 0x497820a }, > > +       { 0x3d400194, 0x80303 }, > > +       { 0x3d4001b4, 0x170a }, > > +       { 0x3d4001a0, 0xe0400018 }, > > +       { 0x3d4001a4, 0xdf00e4 }, > > +       { 0x3d4001a8, 0x80000000 }, > > +       { 0x3d4001b0, 0x11 }, > > +       { 0x3d4001c0, 0x1 }, > > +       { 0x3d4001c4, 0x1 }, > > +       { 0x3d4000f4, 0xc99 }, > > +       { 0x3d400108, 0x70e1617 }, > > +       { 0x3d400200, 0x1f }, > > +       { 0x3d40020c, 0x0 }, > > +       { 0x3d400210, 0x1f1f }, > > +       { 0x3d400204, 0x80808 }, > > +       { 0x3d400214, 0x7070707 }, > > +       { 0x3d400218, 0x7070707 }, > > +       { 0x3d40021c, 0xf0f }, > > +       { 0x3d400250, 0x1705 }, > > +       { 0x3d400254, 0x2c }, > > +       { 0x3d40025c, 0x4000030 }, > > +       { 0x3d400264, 0x900093e7 }, > > +       { 0x3d40026c, 0x2005574 }, > > +       { 0x3d400400, 0x111 }, > > +       { 0x3d400404, 0x72ff }, > > +       { 0x3d400408, 0x72ff }, > > +       { 0x3d400494, 0x2100e07 }, > > +       { 0x3d400498, 0x620096 }, > > +       { 0x3d40049c, 0x1100e07 }, > > +       { 0x3d4004a0, 0xc8012c }, > > +       { 0x3d402020, 0x1021 }, > > +       { 0x3d402024, 0x30d400 }, > > +       { 0x3d402050, 0x20d000 }, > > +       { 0x3d402064, 0xc001c }, > > +       { 0x3d4020dc, 0x840000 }, > > +       { 0x3d4020e0, 0x330000 }, > > +       { 0x3d4020e8, 0x660048 }, > > +       { 0x3d4020ec, 0x160048 }, > > +       { 0x3d402100, 0xa040305 }, > > +       { 0x3d402104, 0x30407 }, > > +       { 0x3d402108, 0x203060b }, > > +       { 0x3d40210c, 0x505000 }, > > +       { 0x3d402110, 0x2040202 }, > > +       { 0x3d402114, 0x2030202 }, > > +       { 0x3d402118, 0x1010004 }, > > +       { 0x3d40211c, 0x301 }, > > +       { 0x3d402130, 0x20300 }, > > +       { 0x3d402134, 0xa100002 }, > > +       { 0x3d402138, 0x1d }, > > +       { 0x3d402144, 0x14000a }, > > +       { 0x3d402180, 0x640004 }, > > +       { 0x3d402190, 0x3818200 }, > > +       { 0x3d402194, 0x80303 }, > > +       { 0x3d4021b4, 0x100 }, > > +       { 0x3d4020f4, 0xc99 }, > > +       { 0x3d403020, 0x1021 }, > > +       { 0x3d403024, 0xc3500 }, > > +       { 0x3d403050, 0x20d000 }, > > +       { 0x3d403064, 0x30007 }, > > +       { 0x3d4030dc, 0x840000 }, > > +       { 0x3d4030e0, 0x330000 }, > > +       { 0x3d4030e8, 0x660048 }, > > +       { 0x3d4030ec, 0x160048 }, > > +       { 0x3d403100, 0xa010102 }, > > +       { 0x3d403104, 0x30404 }, > > +       { 0x3d403108, 0x203060b }, > > +       { 0x3d40310c, 0x505000 }, > > +       { 0x3d403110, 0x2040202 }, > > +       { 0x3d403114, 0x2030202 }, > > +       { 0x3d403118, 0x1010004 }, > > +       { 0x3d40311c, 0x301 }, > > +       { 0x3d403130, 0x20300 }, > > +       { 0x3d403134, 0xa100002 }, > > +       { 0x3d403138, 0x8 }, > > +       { 0x3d403144, 0x50003 }, > > +       { 0x3d403180, 0x190004 }, > > +       { 0x3d403190, 0x3818200 }, > > +       { 0x3d403194, 0x80303 }, > > +       { 0x3d4031b4, 0x100 }, > > +       { 0x3d4030f4, 0xc99 }, > > +       { 0x3d400028, 0x0 }, > > +}; > > + > > +/* PHY Initialize Configuration */ > > +static struct dram_cfg_param ddr_ddrphy_cfg[] = { > > +       { 0x100a0, 0x0 }, > > +       { 0x100a1, 0x1 }, > > +       { 0x100a2, 0x2 }, > > +       { 0x100a3, 0x3 }, > > +       { 0x100a4, 0x4 }, > > +       { 0x100a5, 0x5 }, > > +       { 0x100a6, 0x6 }, > > +       { 0x100a7, 0x7 }, > > +       { 0x110a0, 0x0 }, > > +       { 0x110a1, 0x1 }, > > +       { 0x110a2, 0x3 }, > > +       { 0x110a3, 0x4 }, > > +       { 0x110a4, 0x5 }, > > +       { 0x110a5, 0x2 }, > > +       { 0x110a6, 0x7 }, > > +       { 0x110a7, 0x6 }, > > +       { 0x120a0, 0x0 }, > > +       { 0x120a1, 0x1 }, > > +       { 0x120a2, 0x3 }, > > +       { 0x120a3, 0x2 }, > > +       { 0x120a4, 0x5 }, > > +       { 0x120a5, 0x4 }, > > +       { 0x120a6, 0x7 }, > > +       { 0x120a7, 0x6 }, > > +       { 0x130a0, 0x0 }, > > +       { 0x130a1, 0x1 }, > > +       { 0x130a2, 0x2 }, > > +       { 0x130a3, 0x3 }, > > +       { 0x130a4, 0x4 }, > > +       { 0x130a5, 0x5 }, > > +       { 0x130a6, 0x6 }, > > +       { 0x130a7, 0x7 }, > > +       { 0x1005f, 0x1ff }, > > +       { 0x1015f, 0x1ff }, > > +       { 0x1105f, 0x1ff }, > > +       { 0x1115f, 0x1ff }, > > +       { 0x1205f, 0x1ff }, > > +       { 0x1215f, 0x1ff }, > > +       { 0x1305f, 0x1ff }, > > +       { 0x1315f, 0x1ff }, > > +       { 0x11005f, 0x1ff }, > > +       { 0x11015f, 0x1ff }, > > +       { 0x11105f, 0x1ff }, > > +       { 0x11115f, 0x1ff }, > > +       { 0x11205f, 0x1ff }, > > +       { 0x11215f, 0x1ff }, > > +       { 0x11305f, 0x1ff }, > > +       { 0x11315f, 0x1ff }, > > +       { 0x21005f, 0x1ff }, > > +       { 0x21015f, 0x1ff }, > > +       { 0x21105f, 0x1ff }, > > +       { 0x21115f, 0x1ff }, > > +       { 0x21205f, 0x1ff }, > > +       { 0x21215f, 0x1ff }, > > +       { 0x21305f, 0x1ff }, > > +       { 0x21315f, 0x1ff }, > > +       { 0x55, 0x1ff }, > > +       { 0x1055, 0x1ff }, > > +       { 0x2055, 0x1ff }, > > +       { 0x3055, 0x1ff }, > > +       { 0x4055, 0x1ff }, > > +       { 0x5055, 0x1ff }, > > +       { 0x6055, 0x1ff }, > > +       { 0x7055, 0x1ff }, > > +       { 0x8055, 0x1ff }, > > +       { 0x9055, 0x1ff }, > > +       { 0x200c5, 0x19 }, > > +       { 0x1200c5, 0x7 }, > > +       { 0x2200c5, 0x7 }, > > +       { 0x2002e, 0x2 }, > > +       { 0x12002e, 0x2 }, > > +       { 0x22002e, 0x2 }, > > +       { 0x90204, 0x0 }, > > +       { 0x190204, 0x0 }, > > +       { 0x290204, 0x0 }, > > +       { 0x20024, 0x1e3 }, > > +       { 0x2003a, 0x2 }, > > +       { 0x120024, 0x1e3 }, > > +       { 0x2003a, 0x2 }, > > +       { 0x220024, 0x1e3 }, > > +       { 0x2003a, 0x2 }, > > +       { 0x20056, 0x3 }, > > +       { 0x120056, 0x3 }, > > +       { 0x220056, 0x3 }, > > +       { 0x1004d, 0xe00 }, > > +       { 0x1014d, 0xe00 }, > > +       { 0x1104d, 0xe00 }, > > +       { 0x1114d, 0xe00 }, > > +       { 0x1204d, 0xe00 }, > > +       { 0x1214d, 0xe00 }, > > +       { 0x1304d, 0xe00 }, > > +       { 0x1314d, 0xe00 }, > > +       { 0x11004d, 0xe00 }, > > +       { 0x11014d, 0xe00 }, > > +       { 0x11104d, 0xe00 }, > > +       { 0x11114d, 0xe00 }, > > +       { 0x11204d, 0xe00 }, > > +       { 0x11214d, 0xe00 }, > > +       { 0x11304d, 0xe00 }, > > +       { 0x11314d, 0xe00 }, > > +       { 0x21004d, 0xe00 }, > > +       { 0x21014d, 0xe00 }, > > +       { 0x21104d, 0xe00 }, > > +       { 0x21114d, 0xe00 }, > > +       { 0x21204d, 0xe00 }, > > +       { 0x21214d, 0xe00 }, > > +       { 0x21304d, 0xe00 }, > > +       { 0x21314d, 0xe00 }, > > +       { 0x10049, 0xeba }, > > +       { 0x10149, 0xeba }, > > +       { 0x11049, 0xeba }, > > +       { 0x11149, 0xeba }, > > +       { 0x12049, 0xeba }, > > +       { 0x12149, 0xeba }, > > +       { 0x13049, 0xeba }, > > +       { 0x13149, 0xeba }, > > +       { 0x110049, 0xeba }, > > +       { 0x110149, 0xeba }, > > +       { 0x111049, 0xeba }, > > +       { 0x111149, 0xeba }, > > +       { 0x112049, 0xeba }, > > +       { 0x112149, 0xeba }, > > +       { 0x113049, 0xeba }, > > +       { 0x113149, 0xeba }, > > +       { 0x210049, 0xeba }, > > +       { 0x210149, 0xeba }, > > +       { 0x211049, 0xeba }, > > +       { 0x211149, 0xeba }, > > +       { 0x212049, 0xeba }, > > +       { 0x212149, 0xeba }, > > +       { 0x213049, 0xeba }, > > +       { 0x213149, 0xeba }, > > +       { 0x43, 0x63 }, > > +       { 0x1043, 0x63 }, > > +       { 0x2043, 0x63 }, > > +       { 0x3043, 0x63 }, > > +       { 0x4043, 0x63 }, > > +       { 0x5043, 0x63 }, > > +       { 0x6043, 0x63 }, > > +       { 0x7043, 0x63 }, > > +       { 0x8043, 0x63 }, > > +       { 0x9043, 0x63 }, > > +       { 0x20018, 0x3 }, > > +       { 0x20075, 0x4 }, > > +       { 0x20050, 0x0 }, > > +       { 0x20008, 0x2ee }, > > +       { 0x120008, 0x64 }, > > +       { 0x220008, 0x19 }, > > +       { 0x20088, 0x9 }, > > +       { 0x200b2, 0x104 }, > > +       { 0x10043, 0x5a1 }, > > +       { 0x10143, 0x5a1 }, > > +       { 0x11043, 0x5a1 }, > > +       { 0x11143, 0x5a1 }, > > +       { 0x12043, 0x5a1 }, > > +       { 0x12143, 0x5a1 }, > > +       { 0x13043, 0x5a1 }, > > +       { 0x13143, 0x5a1 }, > > +       { 0x1200b2, 0x104 }, > > +       { 0x110043, 0x5a1 }, > > +       { 0x110143, 0x5a1 }, > > +       { 0x111043, 0x5a1 }, > > +       { 0x111143, 0x5a1 }, > > +       { 0x112043, 0x5a1 }, > > +       { 0x112143, 0x5a1 }, > > +       { 0x113043, 0x5a1 }, > > +       { 0x113143, 0x5a1 }, > > +       { 0x2200b2, 0x104 }, > > +       { 0x210043, 0x5a1 }, > > +       { 0x210143, 0x5a1 }, > > +       { 0x211043, 0x5a1 }, > > +       { 0x211143, 0x5a1 }, > > +       { 0x212043, 0x5a1 }, > > +       { 0x212143, 0x5a1 }, > > +       { 0x213043, 0x5a1 }, > > +       { 0x213143, 0x5a1 }, > > +       { 0x200fa, 0x1 }, > > +       { 0x1200fa, 0x1 }, > > +       { 0x2200fa, 0x1 }, > > +       { 0x20019, 0x1 }, > > +       { 0x120019, 0x1 }, > > +       { 0x220019, 0x1 }, > > +       { 0x200f0, 0x660 }, > > +       { 0x200f1, 0x0 }, > > +       { 0x200f2, 0x4444 }, > > +       { 0x200f3, 0x8888 }, > > +       { 0x200f4, 0x5665 }, > > +       { 0x200f5, 0x0 }, > > +       { 0x200f6, 0x0 }, > > +       { 0x200f7, 0xf000 }, > > +       { 0x20025, 0x0 }, > > +       { 0x2002d, 0x0 }, > > +       { 0x12002d, 0x0 }, > > +       { 0x22002d, 0x0 }, > > +       { 0x2007d, 0x212 }, > > +       { 0x12007d, 0x212 }, > > +       { 0x22007d, 0x212 }, > > +       { 0x2007c, 0x61 }, > > +       { 0x12007c, 0x61 }, > > +       { 0x22007c, 0x61 }, > > +       { 0x1004a, 0x500 }, > > +       { 0x1104a, 0x500 }, > > +       { 0x1204a, 0x500 }, > > +       { 0x1304a, 0x500 }, > > +       { 0x2002c, 0x0 }, > > +}; > > + > > +/* ddr phy trained csr */ > > +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { > > +       { 0x200b2, 0x0 }, > > +       { 0x1200b2, 0x0 }, > > +       { 0x2200b2, 0x0 }, > > +       { 0x200cb, 0x0 }, > > +       { 0x10043, 0x0 }, > > +       { 0x110043, 0x0 }, > > +       { 0x210043, 0x0 }, > > +       { 0x10143, 0x0 }, > > +       { 0x110143, 0x0 }, > > +       { 0x210143, 0x0 }, > > +       { 0x11043, 0x0 }, > > +       { 0x111043, 0x0 }, > > +       { 0x211043, 0x0 }, > > +       { 0x11143, 0x0 }, > > +       { 0x111143, 0x0 }, > > +       { 0x211143, 0x0 }, > > +       { 0x12043, 0x0 }, > > +       { 0x112043, 0x0 }, > > +       { 0x212043, 0x0 }, > > +       { 0x12143, 0x0 }, > > +       { 0x112143, 0x0 }, > > +       { 0x212143, 0x0 }, > > +       { 0x13043, 0x0 }, > > +       { 0x113043, 0x0 }, > > +       { 0x213043, 0x0 }, > > +       { 0x13143, 0x0 }, > > +       { 0x113143, 0x0 }, > > +       { 0x213143, 0x0 }, > > +       { 0x80, 0x0 }, > > +       { 0x100080, 0x0 }, > > +       { 0x200080, 0x0 }, > > +       { 0x1080, 0x0 }, > > +       { 0x101080, 0x0 }, > > +       { 0x201080, 0x0 }, > > +       { 0x2080, 0x0 }, > > +       { 0x102080, 0x0 }, > > +       { 0x202080, 0x0 }, > > +       { 0x3080, 0x0 }, > > +       { 0x103080, 0x0 }, > > +       { 0x203080, 0x0 }, > > +       { 0x4080, 0x0 }, > > +       { 0x104080, 0x0 }, > > +       { 0x204080, 0x0 }, > > +       { 0x5080, 0x0 }, > > +       { 0x105080, 0x0 }, > > +       { 0x205080, 0x0 }, > > +       { 0x6080, 0x0 }, > > +       { 0x106080, 0x0 }, > > +       { 0x206080, 0x0 }, > > +       { 0x7080, 0x0 }, > > +       { 0x107080, 0x0 }, > > +       { 0x207080, 0x0 }, > > +       { 0x8080, 0x0 }, > > +       { 0x108080, 0x0 }, > > +       { 0x208080, 0x0 }, > > +       { 0x9080, 0x0 }, > > +       { 0x109080, 0x0 }, > > +       { 0x209080, 0x0 }, > > +       { 0x10080, 0x0 }, > > +       { 0x110080, 0x0 }, > > +       { 0x210080, 0x0 }, > > +       { 0x10180, 0x0 }, > > +       { 0x110180, 0x0 }, > > +       { 0x210180, 0x0 }, > > +       { 0x11080, 0x0 }, > > +       { 0x111080, 0x0 }, > > +       { 0x211080, 0x0 }, > > +       { 0x11180, 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0x104c1, 0x0 }, > > +       { 0x1104c1, 0x0 }, > > +       { 0x2104c1, 0x0 }, > > +       { 0x105c1, 0x0 }, > > +       { 0x1105c1, 0x0 }, > > +       { 0x2105c1, 0x0 }, > > +       { 0x106c1, 0x0 }, > > +       { 0x1106c1, 0x0 }, > > +       { 0x2106c1, 0x0 }, > > +       { 0x107c1, 0x0 }, > > +       { 0x1107c1, 0x0 }, > > +       { 0x2107c1, 0x0 }, > > +       { 0x108c1, 0x0 }, > > +       { 0x1108c1, 0x0 }, > > +       { 0x2108c1, 0x0 }, > > +       { 0x110c1, 0x0 }, > > +       { 0x1110c1, 0x0 }, > > +       { 0x2110c1, 0x0 }, > > +       { 0x111c1, 0x0 }, > > +       { 0x1111c1, 0x0 }, > > +       { 0x2111c1, 0x0 }, > > +       { 0x112c1, 0x0 }, > > +       { 0x1112c1, 0x0 }, > > +       { 0x2112c1, 0x0 }, > > +       { 0x113c1, 0x0 }, > > +       { 0x1113c1, 0x0 }, > > +       { 0x2113c1, 0x0 }, > > +       { 0x114c1, 0x0 }, > > +       { 0x1114c1, 0x0 }, > > +       { 0x2114c1, 0x0 }, > > +       { 0x115c1, 0x0 }, > > +       { 0x1115c1, 0x0 }, > > +       { 0x2115c1, 0x0 }, > > +       { 0x116c1, 0x0 }, > > +       { 0x1116c1, 0x0 }, > > +       { 0x2116c1, 0x0 }, > > +       { 0x117c1, 0x0 }, > > +       { 0x1117c1, 0x0 }, > > +       { 0x2117c1, 0x0 }, > > +       { 0x118c1, 0x0 }, > > +       { 0x1118c1, 0x0 }, > > +       { 0x2118c1, 0x0 }, > > +       { 0x120c1, 0x0 }, > > +       { 0x1120c1, 0x0 }, > > +       { 0x2120c1, 0x0 }, > > +       { 0x121c1, 0x0 }, > > +       { 0x1121c1, 0x0 }, > > +       { 0x2121c1, 0x0 }, > > +       { 0x122c1, 0x0 }, > > +       { 0x1122c1, 0x0 }, > > +       { 0x2122c1, 0x0 }, > > +       { 0x123c1, 0x0 }, > > +       { 0x1123c1, 0x0 }, > > +       { 0x2123c1, 0x0 }, > > +       { 0x124c1, 0x0 }, > > +       { 0x1124c1, 0x0 }, > > +       { 0x2124c1, 0x0 }, > > +       { 0x125c1, 0x0 }, > > +       { 0x1125c1, 0x0 }, > > +       { 0x2125c1, 0x0 }, > > +       { 0x126c1, 0x0 }, > > +       { 0x1126c1, 0x0 }, > > +       { 0x2126c1, 0x0 }, > > +       { 0x127c1, 0x0 }, > > +       { 0x1127c1, 0x0 }, > > +       { 0x2127c1, 0x0 }, > > +       { 0x128c1, 0x0 }, > > +       { 0x1128c1, 0x0 }, > > +       { 0x2128c1, 0x0 }, > > +       { 0x130c1, 0x0 }, > > +       { 0x1130c1, 0x0 }, > > +       { 0x2130c1, 0x0 }, > > +       { 0x131c1, 0x0 }, > > +       { 0x1131c1, 0x0 }, > > +       { 0x2131c1, 0x0 }, > > +       { 0x132c1, 0x0 }, > > +       { 0x1132c1, 0x0 }, > > +       { 0x2132c1, 0x0 }, > > +       { 0x133c1, 0x0 }, > > +       { 0x1133c1, 0x0 }, > > +       { 0x2133c1, 0x0 }, > > +       { 0x134c1, 0x0 }, > > +       { 0x1134c1, 0x0 }, > > +       { 0x2134c1, 0x0 }, > > +       { 0x135c1, 0x0 }, > > +       { 0x1135c1, 0x0 }, > > +       { 0x2135c1, 0x0 }, > > +       { 0x136c1, 0x0 }, > > +       { 0x1136c1, 0x0 }, > > +       { 0x2136c1, 0x0 }, > > +       { 0x137c1, 0x0 }, > > +       { 0x1137c1, 0x0 }, > > +       { 0x2137c1, 0x0 }, > > +       { 0x138c1, 0x0 }, > > +       { 0x1138c1, 0x0 }, > > +       { 0x2138c1, 0x0 }, > > +       { 0x10020, 0x0 }, > > +       { 0x110020, 0x0 }, > > +       { 0x210020, 0x0 }, > > +       { 0x11020, 0x0 }, > > +       { 0x111020, 0x0 }, > > +       { 0x211020, 0x0 }, > > +       { 0x12020, 0x0 }, > > +       { 0x112020, 0x0 }, > > +       { 0x212020, 0x0 }, > > +       { 0x13020, 0x0 }, > > +       { 0x113020, 0x0 }, > > +       { 0x213020, 0x0 }, > > +       { 0x20072, 0x0 }, > > +       { 0x20073, 0x0 }, > > +       { 0x20074, 0x0 }, > > +       { 0x100aa, 0x0 }, > > +       { 0x110aa, 0x0 }, > > +       { 0x120aa, 0x0 }, > > +       { 0x130aa, 0x0 }, > > +       { 0x20010, 0x0 }, > > +       { 0x120010, 0x0 }, > > +       { 0x220010, 0x0 }, > > +       { 0x20011, 0x0 }, > > +       { 0x120011, 0x0 }, > > +       { 0x220011, 0x0 }, > > +       { 0x100ae, 0x0 }, > > +       { 0x1100ae, 0x0 }, > > +       { 0x2100ae, 0x0 }, > > +       { 0x100af, 0x0 }, > > +       { 0x1100af, 0x0 }, > > +       { 0x2100af, 0x0 }, > > +       { 0x110ae, 0x0 }, > > +       { 0x1110ae, 0x0 }, > > +       { 0x2110ae, 0x0 }, > > +       { 0x110af, 0x0 }, > > +       { 0x1110af, 0x0 }, > > +       { 0x2110af, 0x0 }, > > +       { 0x120ae, 0x0 }, > > +       { 0x1120ae, 0x0 }, > > +       { 0x2120ae, 0x0 }, > > +       { 0x120af, 0x0 }, > > +       { 0x1120af, 0x0 }, > > +       { 0x2120af, 0x0 }, > > +       { 0x130ae, 0x0 }, > > +       { 0x1130ae, 0x0 }, > > +       { 0x2130ae, 0x0 }, > > +       { 0x130af, 0x0 }, > > +       { 0x1130af, 0x0 }, > > +       { 0x2130af, 0x0 }, > > +       { 0x20020, 0x0 }, > > +       { 0x120020, 0x0 }, > > +       { 0x220020, 0x0 }, > > +       { 0x100a0, 0x0 }, > > +       { 0x100a1, 0x0 }, > > +       { 0x100a2, 0x0 }, > > +       { 0x100a3, 0x0 }, > > +       { 0x100a4, 0x0 }, > > +       { 0x100a5, 0x0 }, > > +       { 0x100a6, 0x0 }, > > +       { 0x100a7, 0x0 }, > > +       { 0x110a0, 0x0 }, > > +       { 0x110a1, 0x0 }, > > +       { 0x110a2, 0x0 }, > > +       { 0x110a3, 0x0 }, > > +       { 0x110a4, 0x0 }, > > +       { 0x110a5, 0x0 }, > > +       { 0x110a6, 0x0 }, > > +       { 0x110a7, 0x0 }, > > +       { 0x120a0, 0x0 }, > > +       { 0x120a1, 0x0 }, > > +       { 0x120a2, 0x0 }, > > +       { 0x120a3, 0x0 }, > > +       { 0x120a4, 0x0 }, > > +       { 0x120a5, 0x0 }, > > +       { 0x120a6, 0x0 }, > > +       { 0x120a7, 0x0 }, > > +       { 0x130a0, 0x0 }, > > +       { 0x130a1, 0x0 }, > > +       { 0x130a2, 0x0 }, > > +       { 0x130a3, 0x0 }, > > +       { 0x130a4, 0x0 }, > > +       { 0x130a5, 0x0 }, > > +       { 0x130a6, 0x0 }, > > +       { 0x130a7, 0x0 }, > > +       { 0x2007c, 0x0 }, > > +       { 0x12007c, 0x0 }, > > +       { 0x22007c, 0x0 }, > > +       { 0x2007d, 0x0 }, > > +       { 0x12007d, 0x0 }, > > +       { 0x22007d, 0x0 }, > > +       { 0x400fd, 0x0 }, > > +       { 0x400c0, 0x0 }, > > +       { 0x90201, 0x0 }, > > +       { 0x190201, 0x0 }, > > +       { 0x290201, 0x0 }, > > +       { 0x90202, 0x0 }, > > +       { 0x190202, 0x0 }, > > +       { 0x290202, 0x0 }, > > +       { 0x90203, 0x0 }, > > +       { 0x190203, 0x0 }, > > +       { 0x290203, 0x0 }, > > +       { 0x90204, 0x0 }, > > +       { 0x190204, 0x0 }, > > +       { 0x290204, 0x0 }, > > +       { 0x90205, 0x0 }, > > +       { 0x190205, 0x0 }, > > +       { 0x290205, 0x0 }, > > +       { 0x90206, 0x0 }, > > +       { 0x190206, 0x0 }, > > +       { 0x290206, 0x0 }, > > +       { 0x90207, 0x0 }, > > +       { 0x190207, 0x0 }, > > +       { 0x290207, 0x0 }, > > +       { 0x90208, 0x0 }, > > +       { 0x190208, 0x0 }, > > +       { 0x290208, 0x0 }, > > +       { 0x10062, 0x0 }, > > +       { 0x10162, 0x0 }, > > +       { 0x10262, 0x0 }, > > +       { 0x10362, 0x0 }, > > +       { 0x10462, 0x0 }, > > +       { 0x10562, 0x0 }, > > +       { 0x10662, 0x0 }, > > +       { 0x10762, 0x0 }, > > +       { 0x10862, 0x0 }, > > +       { 0x11062, 0x0 }, > > +       { 0x11162, 0x0 }, > > +       { 0x11262, 0x0 }, > > +       { 0x11362, 0x0 }, > > +       { 0x11462, 0x0 }, > > +       { 0x11562, 0x0 }, > > +       { 0x11662, 0x0 }, > > +       { 0x11762, 0x0 }, > > +       { 0x11862, 0x0 }, > > +       { 0x12062, 0x0 }, > > +       { 0x12162, 0x0 }, > > +       { 0x12262, 0x0 }, > > +       { 0x12362, 0x0 }, > > +       { 0x12462, 0x0 }, > > +       { 0x12562, 0x0 }, > > +       { 0x12662, 0x0 }, > > +       { 0x12762, 0x0 }, > > +       { 0x12862, 0x0 }, > > +       { 0x13062, 0x0 }, > > +       { 0x13162, 0x0 }, > > +       { 0x13262, 0x0 }, > > +       { 0x13362, 0x0 }, > > +       { 0x13462, 0x0 }, > > +       { 0x13562, 0x0 }, > > +       { 0x13662, 0x0 }, > > +       { 0x13762, 0x0 }, > > +       { 0x13862, 0x0 }, > > +       { 0x20077, 0x0 }, > > +       { 0x10001, 0x0 }, > > +       { 0x11001, 0x0 }, > > +       { 0x12001, 0x0 }, > > +       { 0x13001, 0x0 }, > > +       { 0x10040, 0x0 }, > > +       { 0x10140, 0x0 }, > > +       { 0x10240, 0x0 }, > > +       { 0x10340, 0x0 }, > > +       { 0x10440, 0x0 }, > > +       { 0x10540, 0x0 }, > > +       { 0x10640, 0x0 }, > > +       { 0x10740, 0x0 }, > > +       { 0x10840, 0x0 }, > > +       { 0x10030, 0x0 }, > > +       { 0x10130, 0x0 }, > > +       { 0x10230, 0x0 }, > > +       { 0x10330, 0x0 }, > > +       { 0x10430, 0x0 }, > > +       { 0x10530, 0x0 }, > > +       { 0x10630, 0x0 }, > > +       { 0x10730, 0x0 }, > > +       { 0x10830, 0x0 }, > > +       { 0x11040, 0x0 }, > > +       { 0x11140, 0x0 }, > > +       { 0x11240, 0x0 }, > > +       { 0x11340, 0x0 }, > > +       { 0x11440, 0x0 }, > > +       { 0x11540, 0x0 }, > > +       { 0x11640, 0x0 }, > > +       { 0x11740, 0x0 }, > > +       { 0x11840, 0x0 }, > > +       { 0x11030, 0x0 }, > > +       { 0x11130, 0x0 }, > > +       { 0x11230, 0x0 }, > > +       { 0x11330, 0x0 }, > > +       { 0x11430, 0x0 }, > > +       { 0x11530, 0x0 }, > > +       { 0x11630, 0x0 }, > > +       { 0x11730, 0x0 }, > > +       { 0x11830, 0x0 }, > > +       { 0x12040, 0x0 }, > > +       { 0x12140, 0x0 }, > > +       { 0x12240, 0x0 }, > > +       { 0x12340, 0x0 }, > > +       { 0x12440, 0x0 }, > > +       { 0x12540, 0x0 }, > > +       { 0x12640, 0x0 }, > > +       { 0x12740, 0x0 }, > > +       { 0x12840, 0x0 }, > > +       { 0x12030, 0x0 }, > > +       { 0x12130, 0x0 }, > > +       { 0x12230, 0x0 }, > > +       { 0x12330, 0x0 }, > > +       { 0x12430, 0x0 }, > > +       { 0x12530, 0x0 }, > > +       { 0x12630, 0x0 }, > > +       { 0x12730, 0x0 }, > > +       { 0x12830, 0x0 }, > > +       { 0x13040, 0x0 }, > > +       { 0x13140, 0x0 }, > > +       { 0x13240, 0x0 }, > > +       { 0x13340, 0x0 }, > > +       { 0x13440, 0x0 }, > > +       { 0x13540, 0x0 }, > > +       { 0x13640, 0x0 }, > > +       { 0x13740, 0x0 }, > > +       { 0x13840, 0x0 }, > > +       { 0x13030, 0x0 }, > > +       { 0x13130, 0x0 }, > > +       { 0x13230, 0x0 }, > > +       { 0x13330, 0x0 }, > > +       { 0x13430, 0x0 }, > > +       { 0x13530, 0x0 }, > > +       { 0x13630, 0x0 }, > > +       { 0x13730, 0x0 }, > > +       { 0x13830, 0x0 }, > > +}; > > + > > +/* P0 message block paremeter for training firmware */ > > +static struct dram_cfg_param ddr_fsp0_cfg[] = { > > +       { 0xd0000, 0x0 }, > > +       { 0x54003, 0xbb8 }, > > +       { 0x54004, 0x2 }, > > +       { 0x54005, 0x2228 }, > > +       { 0x54006, 0x14 }, > > +       { 0x54008, 0x131f }, > > +       { 0x54009, 0xc8 }, > > +       { 0x5400b, 0x2 }, > > +       { 0x5400f, 0x100 }, > > +       { 0x54012, 0x110 }, > > +       { 0x54019, 0x2dd4 }, > > +       { 0x5401a, 0x33 }, > > +       { 0x5401b, 0x4866 }, > > +       { 0x5401c, 0x4800 }, > > +       { 0x5401e, 0x16 }, > > +       { 0x5401f, 0x2dd4 }, > > +       { 0x54020, 0x33 }, > > +       { 0x54021, 0x4866 }, > > +       { 0x54022, 0x4800 }, > > +       { 0x54024, 0x16 }, > > +       { 0x5402b, 0x1000 }, > > +       { 0x5402c, 0x1 }, > > +       { 0x54032, 0xd400 }, > > +       { 0x54033, 0x332d }, > > +       { 0x54034, 0x6600 }, > > +       { 0x54035, 0x48 }, > > +       { 0x54036, 0x48 }, > > +       { 0x54037, 0x1600 }, > > +       { 0x54038, 0xd400 }, > > +       { 0x54039, 0x332d }, > > +       { 0x5403a, 0x6600 }, > > +       { 0x5403b, 0x48 }, > > +       { 0x5403c, 0x48 }, > > +       { 0x5403d, 0x1600 }, > > +       { 0xd0000, 0x1 }, > > +}; > > + > > +/* P1 message block paremeter for training firmware */ > > +static struct dram_cfg_param ddr_fsp1_cfg[] = { > > +       { 0xd0000, 0x0 }, > > +       { 0x54002, 0x101 }, > > +       { 0x54003, 0x190 }, > > +       { 0x54004, 0x2 }, > > +       { 0x54005, 0x2228 }, > > +       { 0x54006, 0x14 }, > > +       { 0x54008, 0x121f }, > > +       { 0x54009, 0xc8 }, > > +       { 0x5400b, 0x2 }, > > +       { 0x5400f, 0x100 }, > > +       { 0x54012, 0x110 }, > > +       { 0x54019, 0x84 }, > > +       { 0x5401a, 0x33 }, > > +       { 0x5401b, 0x4866 }, > > +       { 0x5401c, 0x4800 }, > > +       { 0x5401e, 0x16 }, > > +       { 0x5401f, 0x84 }, > > +       { 0x54020, 0x33 }, > > +       { 0x54021, 0x4866 }, > > +       { 0x54022, 0x4800 }, > > +       { 0x54024, 0x16 }, > > +       { 0x5402b, 0x1000 }, > > +       { 0x5402c, 0x1 }, > > +       { 0x54032, 0x8400 }, > > +       { 0x54033, 0x3300 }, > > +       { 0x54034, 0x6600 }, > > +       { 0x54035, 0x48 }, > > +       { 0x54036, 0x48 }, > > +       { 0x54037, 0x1600 }, > > +       { 0x54038, 0x8400 }, > > +       { 0x54039, 0x3300 }, > > +       { 0x5403a, 0x6600 }, > > +       { 0x5403b, 0x48 }, > > +       { 0x5403c, 0x48 }, > > +       { 0x5403d, 0x1600 }, > > +       { 0xd0000, 0x1 }, > > +}; > > + > > +/* P2 message block paremeter for training firmware */ > > +static struct dram_cfg_param ddr_fsp2_cfg[] = { > > +       { 0xd0000, 0x0 }, > > +       { 0x54002, 0x102 }, > > +       { 0x54003, 0x64 }, > > +       { 0x54004, 0x2 }, > > +       { 0x54005, 0x2228 }, > > +       { 0x54006, 0x14 }, > > +       { 0x54008, 0x121f }, > > +       { 0x54009, 0xc8 }, > > +       { 0x5400b, 0x2 }, > > +       { 0x5400f, 0x100 }, > > +       { 0x54012, 0x110 }, > > +       { 0x54019, 0x84 }, > > +       { 0x5401a, 0x33 }, > > +       { 0x5401b, 0x4866 }, > > +       { 0x5401c, 0x4800 }, > > +       { 0x5401e, 0x16 }, > > +       { 0x5401f, 0x84 }, > > +       { 0x54020, 0x33 }, > > +       { 0x54021, 0x4866 }, > > +       { 0x54022, 0x4800 }, > > +       { 0x54024, 0x16 }, > > +       { 0x5402b, 0x1000 }, > > +       { 0x5402c, 0x1 }, > > +       { 0x54032, 0x8400 }, > > +       { 0x54033, 0x3300 }, > > +       { 0x54034, 0x6600 }, > > +       { 0x54035, 0x48 }, > > +       { 0x54036, 0x48 }, > > +       { 0x54037, 0x1600 }, > > +       { 0x54038, 0x8400 }, > > +       { 0x54039, 0x3300 }, > > +       { 0x5403a, 0x6600 }, > > +       { 0x5403b, 0x48 }, > > +       { 0x5403c, 0x48 }, > > +       { 0x5403d, 0x1600 }, > > +       { 0xd0000, 0x1 }, > > +}; > > + > > +/* P0 2D message block paremeter for training firmware */ > > +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { > > +       { 0xd0000, 0x0 }, > > +       { 0x54003, 0xbb8 }, > > +       { 0x54004, 0x2 }, > > +       { 0x54005, 0x2228 }, > > +       { 0x54006, 0x14 }, > > +       { 0x54008, 0x61 }, > > +       { 0x54009, 0xc8 }, > > +       { 0x5400b, 0x2 }, > > +       { 0x5400f, 0x100 }, > > +       { 0x54010, 0x1f7f }, > > +       { 0x54012, 0x110 }, > > +       { 0x54019, 0x2dd4 }, > > +       { 0x5401a, 0x33 }, > > +       { 0x5401b, 0x4866 }, > > +       { 0x5401c, 0x4800 }, > > +       { 0x5401e, 0x16 }, > > +       { 0x5401f, 0x2dd4 }, > > +       { 0x54020, 0x33 }, > > +       { 0x54021, 0x4866 }, > > +       { 0x54022, 0x4800 }, > > +       { 0x54024, 0x16 }, > > +       { 0x5402b, 0x1000 }, > > +       { 0x5402c, 0x1 }, > > +       { 0x54032, 0xd400 }, > > +       { 0x54033, 0x332d }, > > +       { 0x54034, 0x6600 }, > > +       { 0x54035, 0x48 }, > > +       { 0x54036, 0x48 }, > > +       { 0x54037, 0x1600 }, > > +       { 0x54038, 0xd400 }, > > +       { 0x54039, 0x332d }, > > +       { 0x5403a, 0x6600 }, > > +       { 0x5403b, 0x48 }, > > +       { 0x5403c, 0x48 }, > > +       { 0x5403d, 0x1600 }, > > +       { 0xd0000, 0x1 }, > > +}; > > + > > +/* DRAM PHY init engine image */ > > +static struct dram_cfg_param ddr_phy_pie[] = { > > +       { 0xd0000, 0x0 }, > > +       { 0x90000, 0x10 }, > > +       { 0x90001, 0x400 }, > > +       { 0x90002, 0x10e }, > > +       { 0x90003, 0x0 }, > > +       { 0x90004, 0x0 }, > > +       { 0x90005, 0x8 }, > > +       { 0x90029, 0xb }, > > +       { 0x9002a, 0x480 }, > > +       { 0x9002b, 0x109 }, > > +       { 0x9002c, 0x8 }, > > +       { 0x9002d, 0x448 }, > > +       { 0x9002e, 0x139 }, > > +       { 0x9002f, 0x8 }, > > +       { 0x90030, 0x478 }, > > +       { 0x90031, 0x109 }, > > +       { 0x90032, 0x0 }, > > +       { 0x90033, 0xe8 }, > > +       { 0x90034, 0x109 }, > > +       { 0x90035, 0x2 }, > > +       { 0x90036, 0x10 }, > > +       { 0x90037, 0x139 }, > > +       { 0x90038, 0xb }, > > +       { 0x90039, 0x7c0 }, > > +       { 0x9003a, 0x139 }, > > +       { 0x9003b, 0x44 }, > > +       { 0x9003c, 0x633 }, > > +       { 0x9003d, 0x159 }, > > +       { 0x9003e, 0x14f }, > > +       { 0x9003f, 0x630 }, > > +       { 0x90040, 0x159 }, > > +       { 0x90041, 0x47 }, > > +       { 0x90042, 0x633 }, > > +       { 0x90043, 0x149 }, > > +       { 0x90044, 0x4f }, > > +       { 0x90045, 0x633 }, > > +       { 0x90046, 0x179 }, > > +       { 0x90047, 0x8 }, > > +       { 0x90048, 0xe0 }, > > +       { 0x90049, 0x109 }, > > +       { 0x9004a, 0x0 }, > > +       { 0x9004b, 0x7c8 }, > > +       { 0x9004c, 0x109 }, > > +       { 0x9004d, 0x0 }, > > +       { 0x9004e, 0x1 }, > > +       { 0x9004f, 0x8 }, > > +       { 0x90050, 0x0 }, > > +       { 0x90051, 0x45a }, > > +       { 0x90052, 0x9 }, > > +       { 0x90053, 0x0 }, > > +       { 0x90054, 0x448 }, > > +       { 0x90055, 0x109 }, > > +       { 0x90056, 0x40 }, > > +       { 0x90057, 0x633 }, > > +       { 0x90058, 0x179 }, > > +       { 0x90059, 0x1 }, > > +       { 0x9005a, 0x618 }, > > +       { 0x9005b, 0x109 }, > > +       { 0x9005c, 0x40c0 }, > > +       { 0x9005d, 0x633 }, > > +       { 0x9005e, 0x149 }, > > +       { 0x9005f, 0x8 }, > > +       { 0x90060, 0x4 }, > > +       { 0x90061, 0x48 }, > > +       { 0x90062, 0x4040 }, > > +       { 0x90063, 0x633 }, > > +       { 0x90064, 0x149 }, > > +       { 0x90065, 0x0 }, > > +       { 0x90066, 0x4 }, > > +       { 0x90067, 0x48 }, > > +       { 0x90068, 0x40 }, > > +       { 0x90069, 0x633 }, > > +       { 0x9006a, 0x149 }, > > +       { 0x9006b, 0x10 }, > > +       { 0x9006c, 0x4 }, > > +       { 0x9006d, 0x18 }, > > +       { 0x9006e, 0x0 }, > > +       { 0x9006f, 0x4 }, > > +       { 0x90070, 0x78 }, > > +       { 0x90071, 0x549 }, > > +       { 0x90072, 0x633 }, > > +       { 0x90073, 0x159 }, > > +       { 0x90074, 0xd49 }, > > +       { 0x90075, 0x633 }, > > +       { 0x90076, 0x159 }, > > +       { 0x90077, 0x94a }, > > +       { 0x90078, 0x633 }, > > +       { 0x90079, 0x159 }, > > +       { 0x9007a, 0x441 }, > > +       { 0x9007b, 0x633 }, > > +       { 0x9007c, 0x149 }, > > +       { 0x9007d, 0x42 }, > > +       { 0x9007e, 0x633 }, > > +       { 0x9007f, 0x149 }, > > +       { 0x90080, 0x1 }, > > +       { 0x90081, 0x633 }, > > +       { 0x90082, 0x149 }, > > +       { 0x90083, 0x0 }, > > +       { 0x90084, 0xe0 }, > > +       { 0x90085, 0x109 }, > > +       { 0x90086, 0xa }, > > +       { 0x90087, 0x10 }, > > +       { 0x90088, 0x109 }, > > +       { 0x90089, 0x9 }, > > +       { 0x9008a, 0x3c0 }, > > +       { 0x9008b, 0x149 }, > > +       { 0x9008c, 0x9 }, > > +       { 0x9008d, 0x3c0 }, > > +       { 0x9008e, 0x159 }, > > +       { 0x9008f, 0x18 }, > > +       { 0x90090, 0x10 }, > > +       { 0x90091, 0x109 }, > > +       { 0x90092, 0x0 }, > > +       { 0x90093, 0x3c0 }, > > +       { 0x90094, 0x109 }, > > +       { 0x90095, 0x18 }, > > +       { 0x90096, 0x4 }, > > +       { 0x90097, 0x48 }, > > +       { 0x90098, 0x18 }, > > +       { 0x90099, 0x4 }, > > +       { 0x9009a, 0x58 }, > > +       { 0x9009b, 0xb }, > > +       { 0x9009c, 0x10 }, > > +       { 0x9009d, 0x109 }, > > +       { 0x9009e, 0x1 }, > > +       { 0x9009f, 0x10 }, > > +       { 0x900a0, 0x109 }, > > +       { 0x900a1, 0x5 }, > > +       { 0x900a2, 0x7c0 }, > > +       { 0x900a3, 0x109 }, > > +       { 0x40000, 0x811 }, > > +       { 0x40020, 0x880 }, > > +       { 0x40040, 0x0 }, > > +       { 0x40060, 0x0 }, > > +       { 0x40001, 0x4008 }, > > +       { 0x40021, 0x83 }, > > +       { 0x40041, 0x4f }, > > +       { 0x40061, 0x0 }, > > +       { 0x40002, 0x4040 }, > > +       { 0x40022, 0x83 }, > > +       { 0x40042, 0x51 }, > > +       { 0x40062, 0x0 }, > > +       { 0x40003, 0x811 }, > > +       { 0x40023, 0x880 }, > > +       { 0x40043, 0x0 }, > > +       { 0x40063, 0x0 }, > > +       { 0x40004, 0x720 }, > > +       { 0x40024, 0xf }, > > +       { 0x40044, 0x1740 }, > > +       { 0x40064, 0x0 }, > > +       { 0x40005, 0x16 }, > > +       { 0x40025, 0x83 }, > > +       { 0x40045, 0x4b }, > > +       { 0x40065, 0x0 }, > > +       { 0x40006, 0x716 }, > > +       { 0x40026, 0xf }, > > +       { 0x40046, 0x2001 }, > > +       { 0x40066, 0x0 }, > > +       { 0x40007, 0x716 }, > > +       { 0x40027, 0xf }, > > +       { 0x40047, 0x2800 }, > > +       { 0x40067, 0x0 }, > > +       { 0x40008, 0x716 }, > > +       { 0x40028, 0xf }, > > +       { 0x40048, 0xf00 }, > > +       { 0x40068, 0x0 }, > > +       { 0x40009, 0x720 }, > > +       { 0x40029, 0xf }, > > +       { 0x40049, 0x1400 }, > > +       { 0x40069, 0x0 }, > > +       { 0x4000a, 0xe08 }, > > +       { 0x4002a, 0xc15 }, > > +       { 0x4004a, 0x0 }, > > +       { 0x4006a, 0x0 }, > > +       { 0x4000b, 0x625 }, > > +       { 0x4002b, 0x15 }, > > +       { 0x4004b, 0x0 }, > > +       { 0x4006b, 0x0 }, > > +       { 0x4000c, 0x4028 }, > > +       { 0x4002c, 0x80 }, > > +       { 0x4004c, 0x0 }, > > +       { 0x4006c, 0x0 }, > > +       { 0x4000d, 0xe08 }, > > +       { 0x4002d, 0xc1a }, > > +       { 0x4004d, 0x0 }, > > +       { 0x4006d, 0x0 }, > > +       { 0x4000e, 0x625 }, > > +       { 0x4002e, 0x1a }, > > +       { 0x4004e, 0x0 }, > > +       { 0x4006e, 0x0 }, > > +       { 0x4000f, 0x4040 }, > > +       { 0x4002f, 0x80 }, > > +       { 0x4004f, 0x0 }, > > +       { 0x4006f, 0x0 }, > > +       { 0x40010, 0x2604 }, > > +       { 0x40030, 0x15 }, > > +       { 0x40050, 0x0 }, > > +       { 0x40070, 0x0 }, > > +       { 0x40011, 0x708 }, > > +       { 0x40031, 0x5 }, > > +       { 0x40051, 0x0 }, > > +       { 0x40071, 0x2002 }, > > +       { 0x40012, 0x8 }, > > +       { 0x40032, 0x80 }, > > +       { 0x40052, 0x0 }, > > +       { 0x40072, 0x0 }, > > +       { 0x40013, 0x2604 }, > > +       { 0x40033, 0x1a }, > > +       { 0x40053, 0x0 }, > > +       { 0x40073, 0x0 }, > > +       { 0x40014, 0x708 }, > > +       { 0x40034, 0xa }, > > +       { 0x40054, 0x0 }, > > +       { 0x40074, 0x2002 }, > > +       { 0x40015, 0x4040 }, > > +       { 0x40035, 0x80 }, > > +       { 0x40055, 0x0 }, > > +       { 0x40075, 0x0 }, > > +       { 0x40016, 0x60a }, > > +       { 0x40036, 0x15 }, > > +       { 0x40056, 0x1200 }, > > +       { 0x40076, 0x0 }, > > +       { 0x40017, 0x61a }, > > +       { 0x40037, 0x15 }, > > +       { 0x40057, 0x1300 }, > > +       { 0x40077, 0x0 }, > > +       { 0x40018, 0x60a }, > > +       { 0x40038, 0x1a }, > > +       { 0x40058, 0x1200 }, > > +       { 0x40078, 0x0 }, > > +       { 0x40019, 0x642 }, > > +       { 0x40039, 0x1a }, > > +       { 0x40059, 0x1300 }, > > +       { 0x40079, 0x0 }, > > +       { 0x4001a, 0x4808 }, > > +       { 0x4003a, 0x880 }, > > +       { 0x4005a, 0x0 }, > > +       { 0x4007a, 0x0 }, > > +       { 0x900a4, 0x0 }, > > +       { 0x900a5, 0x790 }, > > +       { 0x900a6, 0x11a }, > > +       { 0x900a7, 0x8 }, > > +       { 0x900a8, 0x7aa }, > > +       { 0x900a9, 0x2a }, > > +       { 0x900aa, 0x10 }, > > +       { 0x900ab, 0x7b2 }, > > +       { 0x900ac, 0x2a }, > > +       { 0x900ad, 0x0 }, > > +       { 0x900ae, 0x7c8 }, > > +       { 0x900af, 0x109 }, > > +       { 0x900b0, 0x10 }, > > +       { 0x900b1, 0x10 }, > > +       { 0x900b2, 0x109 }, > > +       { 0x900b3, 0x10 }, > > +       { 0x900b4, 0x2a8 }, > > +       { 0x900b5, 0x129 }, > > +       { 0x900b6, 0x8 }, > > +       { 0x900b7, 0x370 }, > > +       { 0x900b8, 0x129 }, > > +       { 0x900b9, 0xa }, > > +       { 0x900ba, 0x3c8 }, > > +       { 0x900bb, 0x1a9 }, > > +       { 0x900bc, 0xc }, > > +       { 0x900bd, 0x408 }, > > +       { 0x900be, 0x199 }, > > +       { 0x900bf, 0x14 }, > > +       { 0x900c0, 0x790 }, > > +       { 0x900c1, 0x11a }, > > +       { 0x900c2, 0x8 }, > > +       { 0x900c3, 0x4 }, > > +       { 0x900c4, 0x18 }, > > +       { 0x900c5, 0xe }, > > +       { 0x900c6, 0x408 }, > > +       { 0x900c7, 0x199 }, > > +       { 0x900c8, 0x8 }, > > +       { 0x900c9, 0x8568 }, > > +       { 0x900ca, 0x108 }, > > +       { 0x900cb, 0x18 }, > > +       { 0x900cc, 0x790 }, > > +       { 0x900cd, 0x16a }, > > +       { 0x900ce, 0x8 }, > > +       { 0x900cf, 0x1d8 }, > > +       { 0x900d0, 0x169 }, > > +       { 0x900d1, 0x10 }, > > +       { 0x900d2, 0x8558 }, > > +       { 0x900d3, 0x168 }, > > +       { 0x900d4, 0x70 }, > > +       { 0x900d5, 0x788 }, > > +       { 0x900d6, 0x16a }, > > +       { 0x900d7, 0x1ff8 }, > > +       { 0x900d8, 0x85a8 }, > > +       { 0x900d9, 0x1e8 }, > > +       { 0x900da, 0x50 }, > > +       { 0x900db, 0x798 }, > > +       { 0x900dc, 0x16a }, > > +       { 0x900dd, 0x60 }, > > +       { 0x900de, 0x7a0 }, > > +       { 0x900df, 0x16a }, > > +       { 0x900e0, 0x8 }, > > +       { 0x900e1, 0x8310 }, > > +       { 0x900e2, 0x168 }, > > +       { 0x900e3, 0x8 }, > > +       { 0x900e4, 0xa310 }, > > +       { 0x900e5, 0x168 }, > > +       { 0x900e6, 0xa }, > > +       { 0x900e7, 0x408 }, > > +       { 0x900e8, 0x169 }, > > +       { 0x900e9, 0x6e }, > > +       { 0x900ea, 0x0 }, > > +       { 0x900eb, 0x68 }, > > +       { 0x900ec, 0x0 }, > > +       { 0x900ed, 0x408 }, > > +       { 0x900ee, 0x169 }, > > +       { 0x900ef, 0x0 }, > > +       { 0x900f0, 0x8310 }, > > +       { 0x900f1, 0x168 }, > > +       { 0x900f2, 0x0 }, > > +       { 0x900f3, 0xa310 }, > > +       { 0x900f4, 0x168 }, > > +       { 0x900f5, 0x1ff8 }, > > +       { 0x900f6, 0x85a8 }, > > +       { 0x900f7, 0x1e8 }, > > +       { 0x900f8, 0x68 }, > > +       { 0x900f9, 0x798 }, > > +       { 0x900fa, 0x16a }, > > +       { 0x900fb, 0x78 }, > > +       { 0x900fc, 0x7a0 }, > > +       { 0x900fd, 0x16a }, > > +       { 0x900fe, 0x68 }, > > +       { 0x900ff, 0x790 }, > > +       { 0x90100, 0x16a }, > > +       { 0x90101, 0x8 }, > > +       { 0x90102, 0x8b10 }, > > +       { 0x90103, 0x168 }, > > +       { 0x90104, 0x8 }, > > +       { 0x90105, 0xab10 }, > > +       { 0x90106, 0x168 }, > > +       { 0x90107, 0xa }, > > +       { 0x90108, 0x408 }, > > +       { 0x90109, 0x169 }, > > +       { 0x9010a, 0x58 }, > > +       { 0x9010b, 0x0 }, > > +       { 0x9010c, 0x68 }, > > +       { 0x9010d, 0x0 }, > > +       { 0x9010e, 0x408 }, > > +       { 0x9010f, 0x169 }, > > +       { 0x90110, 0x0 }, > > +       { 0x90111, 0x8b10 }, > > +       { 0x90112, 0x168 }, > > +       { 0x90113, 0x1 }, > > +       { 0x90114, 0xab10 }, > > +       { 0x90115, 0x168 }, > > +       { 0x90116, 0x0 }, > > +       { 0x90117, 0x1d8 }, > > +       { 0x90118, 0x169 }, > > +       { 0x90119, 0x80 }, > > +       { 0x9011a, 0x790 }, > > +       { 0x9011b, 0x16a }, > > +       { 0x9011c, 0x18 }, > > +       { 0x9011d, 0x7aa }, > > +       { 0x9011e, 0x6a }, > > +       { 0x9011f, 0xa }, > > +       { 0x90120, 0x0 }, > > +       { 0x90121, 0x1e9 }, > > +       { 0x90122, 0x8 }, > > +       { 0x90123, 0x8080 }, > > +       { 0x90124, 0x108 }, > > +       { 0x90125, 0xf }, > > +       { 0x90126, 0x408 }, > > +       { 0x90127, 0x169 }, > > +       { 0x90128, 0xc }, > > +       { 0x90129, 0x0 }, > > +       { 0x9012a, 0x68 }, > > +       { 0x9012b, 0x9 }, > > +       { 0x9012c, 0x0 }, > > +       { 0x9012d, 0x1a9 }, > > +       { 0x9012e, 0x0 }, > > +       { 0x9012f, 0x408 }, > > +       { 0x90130, 0x169 }, > > +       { 0x90131, 0x0 }, > > +       { 0x90132, 0x8080 }, > > +       { 0x90133, 0x108 }, > > +       { 0x90134, 0x8 }, > > +       { 0x90135, 0x7aa }, > > +       { 0x90136, 0x6a }, > > +       { 0x90137, 0x0 }, > > +       { 0x90138, 0x8568 }, > > +       { 0x90139, 0x108 }, > > +       { 0x9013a, 0xb7 }, > > +       { 0x9013b, 0x790 }, > > +       { 0x9013c, 0x16a }, > > +       { 0x9013d, 0x1f }, > > +       { 0x9013e, 0x0 }, > > +       { 0x9013f, 0x68 }, > > +       { 0x90140, 0x8 }, > > +       { 0x90141, 0x8558 }, > > +       { 0x90142, 0x168 }, > > +       { 0x90143, 0xf }, > > +       { 0x90144, 0x408 }, > > +       { 0x90145, 0x169 }, > > +       { 0x90146, 0xd }, > > +       { 0x90147, 0x0 }, > > +       { 0x90148, 0x68 }, > > +       { 0x90149, 0x0 }, > > +       { 0x9014a, 0x408 }, > > +       { 0x9014b, 0x169 }, > > +       { 0x9014c, 0x0 }, > > +       { 0x9014d, 0x8558 }, > > +       { 0x9014e, 0x168 }, > > +       { 0x9014f, 0x8 }, > > +       { 0x90150, 0x3c8 }, > > +       { 0x90151, 0x1a9 }, > > +       { 0x90152, 0x3 }, > > +       { 0x90153, 0x370 }, > > +       { 0x90154, 0x129 }, > > +       { 0x90155, 0x20 }, > > +       { 0x90156, 0x2aa }, > > +       { 0x90157, 0x9 }, > > +       { 0x90158, 0x8 }, > > +       { 0x90159, 0xe8 }, > > +       { 0x9015a, 0x109 }, > > +       { 0x9015b, 0x0 }, > > +       { 0x9015c, 0x8140 }, > > +       { 0x9015d, 0x10c }, > > +       { 0x9015e, 0x10 }, > > +       { 0x9015f, 0x8138 }, > > +       { 0x90160, 0x104 }, > > +       { 0x90161, 0x8 }, > > +       { 0x90162, 0x448 }, > > +       { 0x90163, 0x109 }, > > +       { 0x90164, 0xf }, > > +       { 0x90165, 0x7c0 }, > > +       { 0x90166, 0x109 }, > > +       { 0x90167, 0x0 }, > > +       { 0x90168, 0xe8 }, > > +       { 0x90169, 0x109 }, > > +       { 0x9016a, 0x47 }, > > +       { 0x9016b, 0x630 }, > > +       { 0x9016c, 0x109 }, > > +       { 0x9016d, 0x8 }, > > +       { 0x9016e, 0x618 }, > > +       { 0x9016f, 0x109 }, > > +       { 0x90170, 0x8 }, > > +       { 0x90171, 0xe0 }, > > +       { 0x90172, 0x109 }, > > +       { 0x90173, 0x0 }, > > +       { 0x90174, 0x7c8 }, > > +       { 0x90175, 0x109 }, > > +       { 0x90176, 0x8 }, > > +       { 0x90177, 0x8140 }, > > +       { 0x90178, 0x10c }, > > +       { 0x90179, 0x0 }, > > +       { 0x9017a, 0x478 }, > > +       { 0x9017b, 0x109 }, > > +       { 0x9017c, 0x0 }, > > +       { 0x9017d, 0x1 }, > > +       { 0x9017e, 0x8 }, > > +       { 0x9017f, 0x8 }, > > +       { 0x90180, 0x4 }, > > +       { 0x90181, 0x0 }, > > +       { 0x90006, 0x8 }, > > +       { 0x90007, 0x7c8 }, > > +       { 0x90008, 0x109 }, > > +       { 0x90009, 0x0 }, > > +       { 0x9000a, 0x400 }, > > +       { 0x9000b, 0x106 }, > > +       { 0xd00e7, 0x400 }, > > +       { 0x90017, 0x0 }, > > +       { 0x9001f, 0x29 }, > > +       { 0x90026, 0x68 }, > > +       { 0x400d0, 0x0 }, > > +       { 0x400d1, 0x101 }, > > +       { 0x400d2, 0x105 }, > > +       { 0x400d3, 0x107 }, > > +       { 0x400d4, 0x10f }, > > +       { 0x400d5, 0x202 }, > > +       { 0x400d6, 0x20a }, > > +       { 0x400d7, 0x20b }, > > +       { 0x2003a, 0x2 }, > > +       { 0x200be, 0x3 }, > > +       { 0x2000b, 0x34b }, > > +       { 0x2000c, 0xbb }, > > +       { 0x2000d, 0x753 }, > > +       { 0x2000e, 0x2c }, > > +       { 0x12000b, 0x70 }, > > +       { 0x12000c, 0x19 }, > > +       { 0x12000d, 0xfa }, > > +       { 0x12000e, 0x10 }, > > +       { 0x22000b, 0x1c }, > > +       { 0x22000c, 0x6 }, > > +       { 0x22000d, 0x3e }, > > +       { 0x22000e, 0x10 }, > > +       { 0x9000c, 0x0 }, > > +       { 0x9000d, 0x173 }, > > +       { 0x9000e, 0x60 }, > > +       { 0x9000f, 0x6110 }, > > +       { 0x90010, 0x2152 }, > > +       { 0x90011, 0xdfbd }, > > +       { 0x90012, 0x2060 }, > > +       { 0x90013, 0x6152 }, > > +       { 0x20010, 0x5a }, > > +       { 0x20011, 0x3 }, > > +       { 0x40080, 0xe0 }, > > +       { 0x40081, 0x12 }, > > +       { 0x40082, 0xe0 }, > > +       { 0x40083, 0x12 }, > > +       { 0x40084, 0xe0 }, > > +       { 0x40085, 0x12 }, > > +       { 0x140080, 0xe0 }, > > +       { 0x140081, 0x12 }, > > +       { 0x140082, 0xe0 }, > > +       { 0x140083, 0x12 }, > > +       { 0x140084, 0xe0 }, > > +       { 0x140085, 0x12 }, > > +       { 0x240080, 0xe0 }, > > +       { 0x240081, 0x12 }, > > +       { 0x240082, 0xe0 }, > > +       { 0x240083, 0x12 }, > > +       { 0x240084, 0xe0 }, > > +       { 0x240085, 0x12 }, > > +       { 0x400fd, 0xf }, > > +       { 0x10011, 0x1 }, > > +       { 0x10012, 0x1 }, > > +       { 0x10013, 0x180 }, > > +       { 0x10018, 0x1 }, > > +       { 0x10002, 0x6209 }, > > +       { 0x100b2, 0x1 }, > > +       { 0x101b4, 0x1 }, > > +       { 0x102b4, 0x1 }, > > +       { 0x103b4, 0x1 }, > > +       { 0x104b4, 0x1 }, > > +       { 0x105b4, 0x1 }, > > +       { 0x106b4, 0x1 }, > > +       { 0x107b4, 0x1 }, > > +       { 0x108b4, 0x1 }, > > +       { 0x11011, 0x1 }, > > +       { 0x11012, 0x1 }, > > +       { 0x11013, 0x180 }, > > +       { 0x11018, 0x1 }, > > +       { 0x11002, 0x6209 }, > > +       { 0x110b2, 0x1 }, > > +       { 0x111b4, 0x1 }, > > +       { 0x112b4, 0x1 }, > > +       { 0x113b4, 0x1 }, > > +       { 0x114b4, 0x1 }, > > +       { 0x115b4, 0x1 }, > > +       { 0x116b4, 0x1 }, > > +       { 0x117b4, 0x1 }, > > +       { 0x118b4, 0x1 }, > > +       { 0x12011, 0x1 }, > > +       { 0x12012, 0x1 }, > > +       { 0x12013, 0x180 }, > > +       { 0x12018, 0x1 }, > > +       { 0x12002, 0x6209 }, > > +       { 0x120b2, 0x1 }, > > +       { 0x121b4, 0x1 }, > > +       { 0x122b4, 0x1 }, > > +       { 0x123b4, 0x1 }, > > +       { 0x124b4, 0x1 }, > > +       { 0x125b4, 0x1 }, > > +       { 0x126b4, 0x1 }, > > +       { 0x127b4, 0x1 }, > > +       { 0x128b4, 0x1 }, > > +       { 0x13011, 0x1 }, > > +       { 0x13012, 0x1 }, > > +       { 0x13013, 0x180 }, > > +       { 0x13018, 0x1 }, > > +       { 0x13002, 0x6209 }, > > +       { 0x130b2, 0x1 }, > > +       { 0x131b4, 0x1 }, > > +       { 0x132b4, 0x1 }, > > +       { 0x133b4, 0x1 }, > > +       { 0x134b4, 0x1 }, > > +       { 0x135b4, 0x1 }, > > +       { 0x136b4, 0x1 }, > > +       { 0x137b4, 0x1 }, > > +       { 0x138b4, 0x1 }, > > +       { 0x20089, 0x1 }, > > +       { 0x20088, 0x19 }, > > +       { 0xc0080, 0x2 }, > > +       { 0xd0000, 0x1 } > > +}; > > + > > +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { > > +       { > > +               /* P0 3000mts 1D */ > > +               .drate = 3000, > > +               .fw_type = FW_1D_IMAGE, > > +               .fsp_cfg = ddr_fsp0_cfg, > > +               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), > > +       }, > > +       { > > +               /* P1 400mts 1D */ > > +               .drate = 400, > > +               .fw_type = FW_1D_IMAGE, > > +               .fsp_cfg = ddr_fsp1_cfg, > > +               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), > > +       }, > > +       { > > +               /* P2 100mts 1D */ > > +               .drate = 100, > > +               .fw_type = FW_1D_IMAGE, > > +               .fsp_cfg = ddr_fsp2_cfg, > > +               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), > > +       }, > > +       { > > +               /* P0 3000mts 2D */ > > +               .drate = 3000, > > +               .fw_type = FW_2D_IMAGE, > > +               .fsp_cfg = ddr_fsp0_2d_cfg, > > +               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), > > +       }, > > +}; > > + > > +/* ddr timing config params */ > > +struct dram_timing_info dram_timing = { > > +       .ddrc_cfg = ddr_ddrc_cfg, > > +       .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), > > +       .ddrphy_cfg = ddr_ddrphy_cfg, > > +       .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), > > +       .fsp_msg = ddr_dram_fsp_msg, > > +       .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), > > +       .ddrphy_trained_csr = ddr_ddrphy_trained_csr, > > +       .ddrphy_trained_csr_num = > > ARRAY_SIZE(ddr_ddrphy_trained_csr), > > +       .ddrphy_pie = ddr_phy_pie, > > +       .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), > > +       .fsp_table = { 3000, 400, 100, }, > > +}; > > diff --git a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c > > b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c > > new file mode 100644 > > index 0000000000..3913c4f242 > > --- /dev/null > > +++ b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c > > @@ -0,0 +1,60 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Based on vendor support provided by AVNET Embedded > > + * > > + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH > > + * Copyright 2021 General Electric Company > > + * Copyright 2021 Collabora Ltd. > > + */ > > + > > +#include <common.h> > > +#include <errno.h> > > +#include <miiphy.h> > > +#include <netdev.h> > > +#include <asm/arch/clock.h> > > +#include <asm/arch/imx8mp_pins.h> > > +#include <asm/arch/sys_proto.h> > > +#include <asm/mach-imx/gpio.h> > > +#include <asm/mach-imx/iomux-v3.h> > > +#include <asm-generic/gpio.h> > > +#include <linux/delay.h> > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +static void setup_fec(void) > > +{ > > +       struct iomuxc_gpr_base_regs *gpr = > > +               (struct iomuxc_gpr_base_regs > > *)IOMUXC_GPR_BASE_ADDR; > > + > > +       /* Enable RGMII TX clk output */ > > +       setbits_le32(&gpr->gpr[1], BIT(22)); > > +} > > + > > +static int setup_eqos(void) > > +{ > > +       struct iomuxc_gpr_base_regs *gpr = > > +               (struct iomuxc_gpr_base_regs > > *)IOMUXC_GPR_BASE_ADDR; > > + > > +       /* set INTF as RGMII, enable RGMII TXC clock */ > > +       clrsetbits_le32(&gpr->gpr[1], > > +                       IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, > > BIT(16)); > > +       setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); > > + > > +       return set_clk_eqos(ENET_125MHZ); > > +} > > + > > +int board_phy_config(struct phy_device *phydev) > > +{ > > +       if (phydev->drv->config) > > +               phydev->drv->config(phydev); > > +       return 0; > > +} > > + > > +int board_init(void) > > +{ > > +       setup_fec(); > > + > > +       setup_eqos(); > > + > > +       return 0; > > +} > > diff --git a/board/msc/sm2s_imx8mp/spl.c > > b/board/msc/sm2s_imx8mp/spl.c > > new file mode 100644 > > index 0000000000..d20c9c52c9 > > --- /dev/null > > +++ b/board/msc/sm2s_imx8mp/spl.c > > @@ -0,0 +1,273 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Based on vendor support provided by AVNET Embedded > > + * > > + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH > > + * Copyright 2021 General Electric Company > > + * Copyright 2021 Collabora Ltd. > > + */ > > + > > +#include <common.h> > > +#include <cpu_func.h> > > +#include <fsl_esdhc_imx.h> > > +#include <hang.h> > > +#include <i2c.h> > > +#include <image.h> > > +#include <init.h> > > +#include <log.h> > > +#include <mmc.h> > > +#include <spl.h> > > +#include <asm/global_data.h> > > +#include <asm/io.h> > > +#include <asm/arch/clock.h> > > +#include <asm/arch/ddr.h> > > +#include <asm/arch/imx8mp_pins.h> > > +#include <asm/arch/sys_proto.h> > > +#include <asm/mach-imx/boot_mode.h> > > +#include <asm/mach-imx/gpio.h> > > +#include <asm/mach-imx/iomux-v3.h> > > +#include <asm/mach-imx/mxc_i2c.h> > > +#include <dm/uclass.h> > > +#include <dm/device.h> > > +#include <linux/delay.h> > > +#include <power/pmic.h> > > +#include <power/rn5t567_pmic.h> > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +int spl_board_boot_device(enum boot_device boot_dev_spl) > > +{ > > +       return BOOT_DEVICE_BOOTROM; > > +} > > + > > +void spl_dram_init(void) > > +{ > > +       ddr_init(&dram_timing); > > +} > > + > > +void spl_board_init(void) > > +{ > > +       /* > > +       * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver > > does > > +       * not allow to change it. Should set the clock after PMIC > > +       * setting done. Default is 400Mhz (system_pll1_800m with > > div = 2) > > +       * set by ROM for ND VDD_SOC > > +       */ > > +       clock_enable(CCGR_GIC, 0); > > +       clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | > > CLK_ROOT_SOURCE_SEL(5)); > > +       clock_enable(CCGR_GIC, 1); > > + > > +       puts("Normal Boot\n"); > > +} > > + > > +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE \ > > +       | PAD_CTL_PE | PAD_CTL_FSEL2) > > +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) > > +#define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS > > \ > > +       | PAD_CTL_DSE4) > > + > > +static const iomux_v3_cfg_t usdhc2_pads[] = { > > +       MX8MP_PAD_SD2_CLK__USDHC2_CLK | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_SD2_CMD__USDHC2_CMD | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | > > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), > > +       MX8MP_PAD_SD2_WP__GPIO2_IO20 | > > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), > > +       MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | > > MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), > > +}; > > + > > +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) > > +#define USDHC2_RESET_GPIO IMX_GPIO_NR(2, 19) > > + > > +static const iomux_v3_cfg_t usdhc3_pads[] = { > > +       MX8MP_PAD_NAND_WE_B__USDHC3_CLK | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_NAND_WP_B__USDHC3_CMD | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +       MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + > > +}; > > + > > +static struct fsl_esdhc_cfg usdhc_cfg[] = { > > +       { USDHC2_BASE_ADDR, 0, 4 }, > > +       { USDHC3_BASE_ADDR, 0, 8 }, > > +}; > > + > > +int board_mmc_init(struct bd_info *bis) > > +{ > > +       int i, ret; > > +       /* > > +       * According to the board_mmc_init() the following map is > > done: > > +       * (U-Boot device node)   (Physical Port) > > +       * mmc0 (sd)              USDHC2 > > +       * mmc1 (emmc)            USDHC3 > > +       */ > > +       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { > > +               switch (i) { > > +               case 0: > > +                       init_clk_usdhc(1); > > +                       usdhc_cfg[0].sdhc_clk = > > mxc_get_clock(MXC_ESDHC2_CLK); > > +                       imx_iomux_v3_setup_multiple_pads(usdhc2_pad > > s, > > +                                                       > > ARRAY_SIZE(usdhc2_pads)); > > +                       gpio_request(USDHC2_RESET_GPIO, > > "usdhc2_reset"); > > +                       gpio_direction_output(USDHC2_RESET_GPIO, > > 0); > > +                       udelay(500); > > +                       gpio_direction_output(USDHC2_RESET_GPIO, > > 1); > > +                       gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); > > +                       gpio_direction_input(USDHC2_CD_GPIO); > > +                       break; > > +               case 1: > > +                       init_clk_usdhc(2); > > +                       usdhc_cfg[1].sdhc_clk = > > mxc_get_clock(MXC_ESDHC3_CLK); > > +                       imx_iomux_v3_setup_multiple_pads(usdhc3_pad > > s, > > +                                                       > > ARRAY_SIZE(usdhc3_pads)); > > +                       break; > > +               default: > > +                       printf("Warning: you configured more USDHC > > controllers (%d) than supported by the board\n", > > +                             i + 1); > > +                       return -EINVAL; > > +               } > > + > > +               ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); > > +               if (ret) > > +                       return ret; > > +       } > > + > > +       return 0; > > +} > > + > > +int board_mmc_getcd(struct mmc *mmc) > > +{ > > +       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc- > > >priv; > > +       int ret = 0; > > + > > +       switch (cfg->esdhc_base) { > > +       case USDHC2_BASE_ADDR: > > +               ret = !gpio_get_value(USDHC2_CD_GPIO); > > +               break; > > +       case USDHC3_BASE_ADDR: > > +               ret = 1; > > +               break; > > +       } > > + > > +       return ret; > > +} > > + > > +#define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | > > PAD_CTL_PE) > > + > > +static const iomux_v3_cfg_t wdog_pads[] = { > > +       MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | > > MUX_PAD_CTRL(WDOG_PAD_CTRL), > > +}; > > + > > +#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1) > > + > > +static const iomux_v3_cfg_t ser0_pads[] = { > > +       MX8MP_PAD_UART2_RXD__UART2_DCE_RX | > > MUX_PAD_CTRL(UART_PAD_CTRL), > > +       MX8MP_PAD_UART2_TXD__UART2_DCE_TX | > > MUX_PAD_CTRL(UART_PAD_CTRL), > > +}; > > + > > +int board_early_init_f(void) > > +{ > > +       struct wdog_regs *wdog = (struct wdog_regs > > *)WDOG1_BASE_ADDR; > > + > > +       imx_iomux_v3_setup_multiple_pads(wdog_pads, > > ARRAY_SIZE(wdog_pads)); > > +       set_wdog_reset(wdog); > > + > > +       imx_iomux_v3_setup_multiple_pads(ser0_pads, > > ARRAY_SIZE(ser0_pads)); > > + > > +       return 0; > > +} > > + > > +static const iomux_v3_cfg_t reset_out_pad[] = { > > +       MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 | MUX_PAD_CTRL(0x19) > > +}; > > + > > +#define RESET_OUT_GPIO IMX_GPIO_NR(4, 27) > > + > > +static void pulse_reset_out(void) > > +{ > > +       imx_iomux_v3_setup_multiple_pads(reset_out_pad, > > ARRAY_SIZE(reset_out_pad)); > > + > > +       gpio_request(RESET_OUT_GPIO, "reset_out_gpio"); > > +       gpio_direction_output(RESET_OUT_GPIO, 0); > > +       udelay(10); > > +       gpio_direction_output(RESET_OUT_GPIO, 1); > > +} > > + > > +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | > > PAD_CTL_PE) > > +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) > > +struct i2c_pads_info i2c_dev_pads = { > > +       .scl = { > > +               .i2c_mode = MX8MP_PAD_SAI5_RXFS__I2C6_SCL | PC, > > +               .gpio_mode = MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 | PC, > > +               .gp = IMX_GPIO_NR(3, 19), > > +       }, > > +       .sda = { > > +               .i2c_mode = MX8MP_PAD_SAI5_RXC__I2C6_SDA | PC, > > +               .gpio_mode = MX8MP_PAD_SAI5_RXC__GPIO3_IO20 | PC, > > +               .gp = IMX_GPIO_NR(3, 20), > > +       }, > > +}; > > + > > +int power_init_board(void) > > +{ > > +       struct udevice *dev; > > +       int ret; > > + > > +       ret = uclass_get_device_by_seq(UCLASS_PMIC, 0, &dev); > > +       if (ret) { > > +               printf("Error: Failed to get PMIC\n"); > > +               return ret; > > +       } > > + > > +       /* set VCC_DRAM (buck2) to 1.1V */ > > +       pmic_reg_write(dev, RN5T567_DC2DAC, 0x28); > > + > > +       /* set VCC_ARM (buck2) to 0.95V */ > > +       pmic_reg_write(dev, RN5T567_DC3DAC, 0x1C); > > + > > +       return 0; > > +} > > + > > +int board_fit_config_name_match(const char *name) > > +{ > > +       return 0; > > +} > > + > > +void board_init_f(ulong dummy) > > +{ > > +       int ret; > > + > > +       arch_cpu_init(); > > + > > +       init_uart_clk(1); > > + > > +       board_early_init_f(); > > + > > +       pulse_reset_out(); > > + > > +       timer_init(); > > + > > +       ret = spl_early_init(); > > +       if (ret) { > > +               printf("Error: failed to initialize SPL!\n"); > > +               hang(); > > +       } > > + > > +       preloader_console_init(); > > + > > +       enable_tzc380(); > > + > > +       power_init_board(); > > + > > +       spl_dram_init(); > > +} > > diff --git a/configs/msc_sm2s_imx8mp_defconfig > > b/configs/msc_sm2s_imx8mp_defconfig > > new file mode 100644 > > index 0000000000..82c72a642c > > --- /dev/null > > +++ b/configs/msc_sm2s_imx8mp_defconfig > > @@ -0,0 +1,91 @@ > > +CONFIG_ARM=y > > +CONFIG_ARCH_IMX8M=y > > +CONFIG_SYS_TEXT_BASE=0x40200000 > > +CONFIG_SYS_MALLOC_LEN=0x2000000 > > +CONFIG_SPL_GPIO=y > > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > > +CONFIG_ENV_SIZE=0x1000 > > +CONFIG_DM_GPIO=y > > +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-msc-sm2s" > > +CONFIG_SPL_TEXT_BASE=0x920000 > > +CONFIG_TARGET_MSC_SM2S_IMX8MP=y > > +CONFIG_SPL_MMC=y > > +CONFIG_SPL_SERIAL=y > > +CONFIG_SPL_DRIVERS_MISC=y > > +CONFIG_SPL=y > > +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 > > +CONFIG_SYS_LOAD_ADDR=0x40480000 > > +CONFIG_DISTRO_DEFAULTS=y > > +CONFIG_FIT=y > > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 > > +CONFIG_SPL_LOAD_FIT=y > > +# CONFIG_USE_SPL_FIT_GENERATOR is not set > > +CONFIG_OF_SYSTEM_SETUP=y > > +CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb" > > +CONFIG_SPL_MAX_SIZE=0x26000 > > +CONFIG_SPL_BSS_MAX_SIZE=0x400 > > +CONFIG_SPL_BOARD_INIT=y > > +CONFIG_SPL_BOOTROM_SUPPORT=y > > +CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > +CONFIG_SPL_I2C=y > > +CONFIG_SPL_POWER=y > > +CONFIG_SPL_WATCHDOG=y > > +CONFIG_SYS_PROMPT="u-boot=> " > > +CONFIG_SYS_MAXARGS=64 > > +CONFIG_SYS_CBSIZE=2048 > > +CONFIG_SYS_PBSIZE=2074 > > +CONFIG_SYS_BOOTM_LEN=0x2000000 > > +# CONFIG_CMD_EXPORTENV is not set > > +# CONFIG_CMD_IMPORTENV is not set > > +# CONFIG_CMD_CRC32 is not set > > +CONFIG_CMD_CLK=y > > +CONFIG_CMD_FUSE=y > > +CONFIG_CMD_GPIO=y > > +CONFIG_CMD_I2C=y > > +CONFIG_CMD_MMC=y > > +CONFIG_CMD_CACHE=y > > +CONFIG_CMD_REGULATOR=y > > +CONFIG_CMD_EXT4_WRITE=y > > +CONFIG_OF_CONTROL=y > > +CONFIG_SPL_OF_CONTROL=y > > +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts" > > +CONFIG_ENV_OVERWRITE=y > > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > > +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y > > +CONFIG_SPL_DM=y > > +CONFIG_SPL_CLK_COMPOSITE_CCF=y > > +CONFIG_CLK_COMPOSITE_CCF=y > > +CONFIG_SPL_CLK_IMX8MP=y > > +CONFIG_CLK_IMX8MP=y > > +CONFIG_MXC_GPIO=y > > +CONFIG_DM_I2C=y > > +CONFIG_LED=y > > +CONFIG_LED_GPIO=y > > +CONFIG_SUPPORT_EMMC_BOOT=y > > +CONFIG_MMC_IO_VOLTAGE=y > > +CONFIG_MMC_UHS_SUPPORT=y > > +CONFIG_MMC_HS400_ES_SUPPORT=y > > +CONFIG_MMC_HS400_SUPPORT=y > > +CONFIG_FSL_USDHC=y > > +CONFIG_PHY_TI=y > > +CONFIG_DM_ETH=y > > +CONFIG_DM_ETH_PHY=y > > +CONFIG_PHY_GIGE=y > > +CONFIG_DWC_ETH_QOS=y > > +CONFIG_DWC_ETH_QOS_IMX=y > > +CONFIG_FEC_MXC=y > > +CONFIG_MII=y > > +CONFIG_PINCTRL=y > > +CONFIG_SPL_PINCTRL=y > > +CONFIG_PINCTRL_IMX8M=y > > +CONFIG_DM_PMIC=y > > +CONFIG_PMIC_RN5T567=y > > +CONFIG_SPL_PMIC_RN5T567=y > > +CONFIG_DM_REGULATOR=y > > +CONFIG_DM_REGULATOR_FIXED=y > > +CONFIG_DM_REGULATOR_GPIO=y > > +CONFIG_MXC_UART=y > > +CONFIG_SYSRESET=y > > +CONFIG_SPL_SYSRESET=y > > +CONFIG_SYSRESET_PSCI=y > > diff --git a/include/configs/msc_sm2s_imx8mp.h > > b/include/configs/msc_sm2s_imx8mp.h > > new file mode 100644 > > index 0000000000..42be0544ee > > --- /dev/null > > +++ b/include/configs/msc_sm2s_imx8mp.h > > @@ -0,0 +1,96 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Based on vendor support provided by AVNET Embedded > > + * > > + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH > > + * Copyright 2021 General Electric Company > > + * Copyright 2021 Collabora Ltd. > > + */ > > + > > +#ifndef __MSC_SM2S_IMX8MP_H > > +#define __MSC_SM2S_IMX8MP_H > > + > > +#include <linux/sizes.h> > > +#include <linux/stringify.h> > > +#include <asm/arch/imx-regs.h> > > + > > +#define CONFIG_SYS_MONITOR_LEN         (512 * 1024) > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR        0x300 > > +#define CONFIG_SYS_UBOOT_BASE  (QSPI0_AMBA_BASE + > > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > > + > > +#ifdef CONFIG_SPL_BUILD > > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ > > +#define CONFIG_SPL_STACK               0x960000 > > +#define CONFIG_SPL_BSS_START_ADDR      0x0098FC00 > > +#define CONFIG_SYS_SPL_MALLOC_START    0x42200000 > > +#define CONFIG_SYS_SPL_MALLOC_SIZE     SZ_512K /* 512 KB */ > > + > > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE > > + > > +#endif > > + > > +#if defined(CONFIG_CMD_NET) > > +#define CONFIG_ETHPRIME                "eth1" /* Set eqos to > > primary since we use its MDIO */ > > + > > +#define CONFIG_FEC_XCV_TYPE            RGMII > > +#define CONFIG_FEC_MXC_PHYADDR         1 > > +#define FEC_QUIRK_ENET_MAC > > + > > +#define DWC_NET_PHYADDR                        1 > > + > > +#define PHY_ANEG_TIMEOUT 20000 > > + > > +#endif > > + > > +#ifndef CONFIG_SPL_BUILD > > +#define BOOT_TARGET_DEVICES(func) \ > > +       func(MMC, mmc, 1) \ > > +       func(MMC, mmc, 2) > > + > > +#include <config_distro_bootcmd.h> > > +#endif > > + > > +/* Initial environment variables */ > > +#define CONFIG_EXTRA_ENV_SETTINGS              \ > > +       BOOTENV \ > > +       "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > > +       "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > > +       "image=Image\0" \ > > +       "console=ttymxc1,115200\0" \ > > +       "fdt_addr_r=0x43000000\0"                       \ > > +       "boot_fdt=try\0" \ > > +       "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ > > +       "initrd_addr=0x43800000\0"              \ > > +       "bootm_size=0x10000000\0" \ > > +       "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ > > +       "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ > > + > > +/* Link Definitions */ > > + > > +#define CONFIG_SYS_INIT_RAM_ADDR       0x40000000 > > +#define CONFIG_SYS_INIT_RAM_SIZE       0x80000 > > +#define CONFIG_SYS_INIT_SP_OFFSET \ > > +       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > > +#define CONFIG_SYS_INIT_SP_ADDR \ > > +       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > > + > > +#define CONFIG_MMCROOT                 "/dev/mmcblk1p2" /* USDHC2 > > */ > > + > > +#define CONFIG_SYS_SDRAM_BASE          0x40000000 > > +#define PHYS_SDRAM                     0x40000000 > > +#define PHYS_SDRAM_SIZE                        0x80000000 /* 2GB > > DDR */ > > +#define PHYS_SDRAM_2                   0xc0000000 > > +#define PHYS_SDRAM_2_SIZE              0x0 > > + > > +#define CONFIG_MXC_UART_BASE           UART2_BASE_ADDR > > + > > +/* Monitor Command Prompt */ > > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > > + > > +#define CONFIG_SYS_FSL_USDHC_NUM       2 > > +#define CONFIG_SYS_FSL_ESDHC_ADDR      0 > > + > > +#define CONFIG_SYS_MMC_IMG_LOAD_PART   1 > > + > > +#endif >
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 965895bc2a..a5de6e1b5e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -970,6 +970,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-phanbell.dtb \ imx8mp-dhcom-pdk2.dtb \ imx8mp-evk.dtb \ + imx8mp-msc-sm2s.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-venice.dtb \ imx8mp-venice-gw74xx.dtb \ diff --git a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi new file mode 100644 index 0000000000..cf591adf5a --- /dev/null +++ b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + model = "MSC SM2S-IMX8MPLUS"; + compatible = "avnet,sm2s-imx8mp", "fsl,imx8mp"; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&i2c4 { + u-boot,dm-spl; +}; + +&i2c5 { + u-boot,dm-spl; +}; + +&i2c6 { + u-boot,dm-spl; +}; + +&pinctrl_i2c6 { + u-boot,dm-spl; +}; + +&pmic { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mp-msc-sm2s.dts b/arch/arm/dts/imx8mp-msc-sm2s.dts new file mode 100644 index 0000000000..5dbec71747 --- /dev/null +++ b/arch/arm/dts/imx8mp-msc-sm2s.dts @@ -0,0 +1,820 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Avnet Embedded GmbH + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include <dt-bindings/net/ti-dp83867.h> + +/ { + aliases { + rtc0 = &sys_rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart2; + }; + + reg_usb0_host_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_host_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_host_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_flexcan1_xceiver: regulator-flexcan1 { + compatible = "regulator-fixed"; + regulator-name = "flexcan1-xceiver"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_flexcan2_xceiver: regulator-flexcan2 { + compatible = "regulator-fixed"; + regulator-name = "flexcan2-xceiver"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + lcd0_backlight: backlight-0 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_backlight>; + pwms = <&pwm1 0 100000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <255>; + enable-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + lcd1_backlight: backlight-1 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd1_backlight>; + pwms = <&pwm2 0 100000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <255>; + enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + status = "okay"; + + led-sw { + label = "sw-led"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; + + extcon_usb0: extcon-usb0 { + compatible = "linux,extcon-usb-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_extcon>; + id-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&A53_0 { + cpu-supply = <&vcc_arm>; +}; + +&A53_1 { + cpu-supply = <&vcc_arm>; +}; + +&A53_2 { + cpu-supply = <&vcc_arm>; +}; + +&A53_3 { + cpu-supply = <&vcc_arm>; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <0>, <&gpio2 8 GPIO_ACTIVE_LOW>; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <0>, <&gpio2 9 GPIO_ACTIVE_LOW>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + reset-gpios = <&tca6424 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + reset-gpios = <&tca6424 17 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + id_eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "disabled"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "disabled"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <400000>; + status = "disabled"; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5>; + clock-frequency = <400000>; + status = "disabled"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6>; + clock-frequency = <400000>; + status = "okay"; + + tca6424: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tca6424>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BOOT_SEL0#", "BOOT_SEL1#", "BOOT_SEL2#", + "gbe0_int", "gbe1_int", "pmic_int", "rtc_int", "lvds_int", + "PCIE_WAKE#", "cam2_rst", "cam2_pwr", "SLEEP#", + "wifi_pd", "tpm_int", "wifi_int", "PCIE_A_RST#", + "gbe0_rst", "gbe1_rst", "LID#", "BATLOW#", "CHARGING#", + "CHARGER_PRSNT#"; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + dsi_lvds_bridge: bridge@2d { + compatible = "ti,sn65dsi83"; + reg = <0x2d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_bridge>; + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + pmic: pmic@30 { + compatible = "ricoh,rn5t567"; + reg = <0x30>; + interrupt-parent = <&tca6424>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + + regulators { + DCDC1 { + regulator-name = "VCC_SOC"; + regulator-always-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + }; + + DCDC2 { + regulator-name = "VCC_DRAM"; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vcc_arm: DCDC3 { + regulator-name = "VCC_ARM"; + regulator-always-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + }; + + DCDC4 { + regulator-name = "VCC_1V8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + LDO1 { + regulator-name = "VCC_LDO1_2V5"; + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + LDO2 { + regulator-name = "VCC_LDO2_1V8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + LDO3 { + regulator-name = "VCC_ETH_2V5"; + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + LDO4 { + regulator-name = "VCC_DDR4_2V5"; + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + LDO5 { + regulator-name = "VCC_LDO5_1V8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + LDORTC1 { + regulator-name = "VCC_SNVS_1V8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + LDORTC2 { + regulator-name = "VCC_SNVS_3V3"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + sys_rtc: rtc@32 { + compatible = "ricoh,r2221tl"; + reg = <0x32>; + interrupt-parent = <&tca6424>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + }; + + tmp_sensor: temperature-sensor@71 { + compatible = "ti,tmp103"; + reg = <0x71>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_flexcan1_xceiver>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_flexcan2_xceiver>; + status = "disabled"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + qspi_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "disabled"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +&usb3_phy0 { + vbus-supply = <®_usb0_host_vbus>; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_usb1_host_vbus>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + extcon = <&extcon_usb0>; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = + <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82>, + <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82>, + <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82>, + <MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x40000>, + <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x40000>; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = + <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82>, + <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82>, + <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82>, + <MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x40000>, + <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x40000>; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = + <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>, + <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>, + <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>, + <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>, + <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>, + <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>, + <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>, + <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>, + <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>, + <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>, + <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>, + <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>, + <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>, + <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>; + }; + + pinctrl_fec: fecgrp { + fsl,pins = + <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, + <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, + <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, + <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, + <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, + <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, + <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, + <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, + <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, + <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, + <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, + <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, + <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, + <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = + <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154>, + <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154>; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = + <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154>, + <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154>; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = + <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, + <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, + <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, + <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, + <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, + <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, + <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x19>; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = + <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3>, + <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3>; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = + <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3>, + <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3>; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = + <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3>, + <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3>; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = + <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3>, + <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3>; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = + <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3>, + <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3>; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = + <MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3>, + <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3>; + }; + + pinctrl_lcd0_backlight: lcd0-backlightgrp { + fsl,pins = + <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41>; + }; + + pinctrl_lcd1_backlight: lcd1-backlightgrp { + fsl,pins = + <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x41>; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = + <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19>; + }; + + pinctrl_lvds_bridge: lvds-bridgegrp { + fsl,pins = + <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x41>; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = + <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116>; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = + <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116>; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = + <MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x116>; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = + <MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116>; + }; + + pinctrl_tca6424: tca6424grp { + fsl,pins = + <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x41>; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = + <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49>, + <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49>; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = + <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x1c4>, + <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x1c4>, + <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49>, + <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49>; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = + <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>, + <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x1c4>, + <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49>, + <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49>; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = + <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49>, + <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49>; + }; + + pinctrl_usb0_extcon: usb0-extcongrp { + fsl,pins = + <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x19>; + }; + + pinctrl_usb0_vbus: usb0-vbusgrp { + fsl,pins = + <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19>; + }; + + pinctrl_usb1_vbus: usb1-vbusgrp { + fsl,pins = + <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19>; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = + <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>, + <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4>; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = + <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>, + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>; + }; + + pinctrl_usdhc2_vmmc: usdhc2-vmmcgrp { + fsl,pins = + <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41>; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = + <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = + <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>, + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = + <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>, + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = + <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = + <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>, + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6>, + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6>, + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6>, + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6>, + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6>, + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6>, + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6>, + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6>, + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = + <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 3470160990..ee62b958a8 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -270,6 +270,13 @@ config TARGET_IMX8MP_RSB3720A1_6G select SUPPORT_SPL select IMX8M_LPDDR4 +config TARGET_MSC_SM2S_IMX8MP + bool "MSC SMARC2 i.MX8MPLUS" + select BINMAN + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + config TARGET_LIBREM5 bool "Purism Librem5 Phone" select BINMAN @@ -296,6 +303,7 @@ source "board/google/imx8mq_phanbell/Kconfig" source "board/kontron/pitx_imx8m/Kconfig" source "board/kontron/sl-mx8mm/Kconfig" source "board/menlo/mx8menlo/Kconfig" +source "board/msc/sm2s_imx8mp/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/purism/librem5/Kconfig" diff --git a/board/msc/sm2s_imx8mp/Kconfig b/board/msc/sm2s_imx8mp/Kconfig new file mode 100644 index 0000000000..f71a5b2bcd --- /dev/null +++ b/board/msc/sm2s_imx8mp/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MSC_SM2S_IMX8MP + +config SYS_BOARD + default "sm2s_imx8mp" + +config SYS_VENDOR + default "msc" + +config SYS_CONFIG_NAME + default "msc_sm2s_imx8mp" + +config IMX_CONFIG + default "board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg" + +endif diff --git a/board/msc/sm2s_imx8mp/Makefile b/board/msc/sm2s_imx8mp/Makefile new file mode 100644 index 0000000000..f60dd7260c --- /dev/null +++ b/board/msc/sm2s_imx8mp/Makefile @@ -0,0 +1,12 @@ +# +# Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH +# +# SPDX-License-Identifier: GPL-2.0 +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o lpddr4_timing.o +else +obj-y += sm2s_imx8mp.o +endif + diff --git a/board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg b/board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg new file mode 100644 index 0000000000..8aadedb102 --- /dev/null +++ b/board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/msc/sm2s_imx8mp/lpddr4_timing.c b/board/msc/sm2s_imx8mp/lpddr4_timing.c new file mode 100644 index 0000000000..e0d659af91 --- /dev/null +++ b/board/msc/sm2s_imx8mp/lpddr4_timing.c @@ -0,0 +1,1842 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d400070, 0x61027f10 }, + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x332d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x332d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x332d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x332d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x34b }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x70 }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x1c }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c new file mode 100644 index 0000000000..3913c4f242 --- /dev/null +++ b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Based on vendor support provided by AVNET Embedded + * + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH + * Copyright 2021 General Electric Company + * Copyright 2021 Collabora Ltd. + */ + +#include <common.h> +#include <errno.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx8mp_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm-generic/gpio.h> +#include <linux/delay.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); +} + +static int setup_eqos(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* set INTF as RGMII, enable RGMII TXC clock */ + clrsetbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); + setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); + + return set_clk_eqos(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} + +int board_init(void) +{ + setup_fec(); + + setup_eqos(); + + return 0; +} diff --git a/board/msc/sm2s_imx8mp/spl.c b/board/msc/sm2s_imx8mp/spl.c new file mode 100644 index 0000000000..d20c9c52c9 --- /dev/null +++ b/board/msc/sm2s_imx8mp/spl.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Based on vendor support provided by AVNET Embedded + * + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH + * Copyright 2021 General Electric Company + * Copyright 2021 Collabora Ltd. + */ + +#include <common.h> +#include <cpu_func.h> +#include <fsl_esdhc_imx.h> +#include <hang.h> +#include <i2c.h> +#include <image.h> +#include <init.h> +#include <log.h> +#include <mmc.h> +#include <spl.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8mp_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <linux/delay.h> +#include <power/pmic.h> +#include <power/rn5t567_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + /* + * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does + * not allow to change it. Should set the clock after PMIC + * setting done. Default is 400Mhz (system_pll1_800m with div = 2) + * set by ROM for ND VDD_SOC + */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); + + puts("Normal Boot\n"); +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE \ + | PAD_CTL_PE | PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) +#define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS \ + | PAD_CTL_DSE4) + +static const iomux_v3_cfg_t usdhc2_pads[] = { + MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC2_RESET_GPIO IMX_GPIO_NR(2, 19) + +static const iomux_v3_cfg_t usdhc3_pads[] = { + MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), + +}; + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { USDHC2_BASE_ADDR, 0, 4 }, + { USDHC3_BASE_ADDR, 0, 8 }, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 (sd) USDHC2 + * mmc1 (emmc) USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_RESET_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_RESET_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_RESET_GPIO, 1); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + case 1: + init_clk_usdhc(2); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, + ARRAY_SIZE(usdhc3_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", + i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = 1; + break; + } + + return ret; +} + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static const iomux_v3_cfg_t wdog_pads[] = { + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +static const iomux_v3_cfg_t ser0_pads[] = { + MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(ser0_pads, ARRAY_SIZE(ser0_pads)); + + return 0; +} + +static const iomux_v3_cfg_t reset_out_pad[] = { + MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 | MUX_PAD_CTRL(0x19) +}; + +#define RESET_OUT_GPIO IMX_GPIO_NR(4, 27) + +static void pulse_reset_out(void) +{ + imx_iomux_v3_setup_multiple_pads(reset_out_pad, ARRAY_SIZE(reset_out_pad)); + + gpio_request(RESET_OUT_GPIO, "reset_out_gpio"); + gpio_direction_output(RESET_OUT_GPIO, 0); + udelay(10); + gpio_direction_output(RESET_OUT_GPIO, 1); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_dev_pads = { + .scl = { + .i2c_mode = MX8MP_PAD_SAI5_RXFS__I2C6_SCL | PC, + .gpio_mode = MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 | PC, + .gp = IMX_GPIO_NR(3, 19), + }, + .sda = { + .i2c_mode = MX8MP_PAD_SAI5_RXC__I2C6_SDA | PC, + .gpio_mode = MX8MP_PAD_SAI5_RXC__GPIO3_IO20 | PC, + .gp = IMX_GPIO_NR(3, 20), + }, +}; + +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_PMIC, 0, &dev); + if (ret) { + printf("Error: Failed to get PMIC\n"); + return ret; + } + + /* set VCC_DRAM (buck2) to 1.1V */ + pmic_reg_write(dev, RN5T567_DC2DAC, 0x28); + + /* set VCC_ARM (buck2) to 0.95V */ + pmic_reg_write(dev, RN5T567_DC3DAC, 0x1C); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + init_uart_clk(1); + + board_early_init_f(); + + pulse_reset_out(); + + timer_init(); + + ret = spl_early_init(); + if (ret) { + printf("Error: failed to initialize SPL!\n"); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + power_init_board(); + + spl_dram_init(); +} diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig new file mode 100644 index 0000000000..82c72a642c --- /dev/null +++ b/configs/msc_sm2s_imx8mp_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-msc-sm2s" +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_MSC_SM2S_IMX8MP=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb" +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts" +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_TI=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RN5T567=y +CONFIG_SPL_PMIC_RN5T567=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h new file mode 100644 index 0000000000..42be0544ee --- /dev/null +++ b/include/configs/msc_sm2s_imx8mp.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Based on vendor support provided by AVNET Embedded + * + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH + * Copyright 2021 General Electric Company + * Copyright 2021 Collabora Ltd. + */ + +#ifndef __MSC_SM2S_IMX8MP_H +#define __MSC_SM2S_IMX8MP_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_STACK 0x960000 +#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */ + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 1 +#define FEC_QUIRK_ENET_MAC + +#define DWC_NET_PHYADDR 1 + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include <config_distro_bootcmd.h> +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + +/* Link Definitions */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#define PHYS_SDRAM_2 0xc0000000 +#define PHYS_SDRAM_2_SIZE 0x0 + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#endif
Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction with the MSC SM2-MB-EP1 Mini-ITX Carrier Board. Signed-off-by: Martyn Welch <martyn.welch@collabora.com> --- Changes in v2: - Renamed FDT to closer match kernel - Sync with kernel FDT - Update for changes made in U-Boot Changes in v3: - Use imx8mp-u-boot.dtsi - Switch to use of DM PMIC support in SPL Changes in v4: - Rebased to latest imx master branch arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi | 65 + arch/arm/dts/imx8mp-msc-sm2s.dts | 820 ++++++++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/msc/sm2s_imx8mp/Kconfig | 15 + board/msc/sm2s_imx8mp/Makefile | 12 + board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg | 8 + board/msc/sm2s_imx8mp/lpddr4_timing.c | 1842 +++++++++++++++++ board/msc/sm2s_imx8mp/sm2s_imx8mp.c | 60 + board/msc/sm2s_imx8mp/spl.c | 273 +++ configs/msc_sm2s_imx8mp_defconfig | 91 + include/configs/msc_sm2s_imx8mp.h | 96 + 12 files changed, 3291 insertions(+) create mode 100644 arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-msc-sm2s.dts create mode 100644 board/msc/sm2s_imx8mp/Kconfig create mode 100644 board/msc/sm2s_imx8mp/Makefile create mode 100644 board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg create mode 100644 board/msc/sm2s_imx8mp/lpddr4_timing.c create mode 100644 board/msc/sm2s_imx8mp/sm2s_imx8mp.c create mode 100644 board/msc/sm2s_imx8mp/spl.c create mode 100644 configs/msc_sm2s_imx8mp_defconfig create mode 100644 include/configs/msc_sm2s_imx8mp.h