diff mbox series

arm: socfpga: Add watchdog 1 support to A10

Message ID 20220919011155.30044-1-teik.heng.chong@intel.com
State Needs Review / ACK, archived
Delegated to: Marek Vasut
Headers show
Series arm: socfpga: Add watchdog 1 support to A10 | expand

Commit Message

Chong, Teik Heng Sept. 19, 2022, 1:11 a.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

Add watchdog 1 support to A10, ensure the same enable/disable process as
watchdog 0.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
---
 .../mach-socfpga/include/mach/base_addr_a10.h |  1 +
 .../include/mach/reset_manager_arria10.h      |  1 +
 arch/arm/mach-socfpga/reset_manager_arria10.c | 21 ++++++++++++++-----
 arch/arm/mach-socfpga/spl_a10.c               |  2 +-
 4 files changed, 19 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index b947cc0729..246618f4da 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -17,6 +17,7 @@ 
 #define SOCFPGA_FPGAMGRDATA_ADDRESS		0xffcfe400
 #define SOCFPGA_FPGAMGRREGS_ADDRESS		0xffd03000
 #define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
 #define SOCFPGA_SYSMGR_ADDRESS			0xffd06000
 #define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS	0xffd07000
 #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd07200
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 9aacf3e2c6..53efb64234 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -13,6 +13,7 @@  void socfpga_watchdog_disable(void);
 void socfpga_reset_deassert_noc_ddr_scheduler(void);
 int socfpga_reset_deassert_bridges_handoff(void);
 void socfpga_reset_deassert_wd0(void);
+void socfpga_reset_deassert_wd1(void);
 int socfpga_bridges_reset(void);
 
 #define RSTMGR_A10_STATUS	0x00
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 13a5cf314b..25c7291246 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -61,6 +61,9 @@  void socfpga_watchdog_disable(void)
 	/* assert reset for watchdog */
 	setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
 		     ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
+
+	setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
+		     ALT_RSTMGR_PER1MODRST_WD1_SET_MSK);
 }
 
 /* Release NOC ddr scheduler from reset */
@@ -116,6 +119,13 @@  void socfpga_reset_deassert_wd0(void)
 		     ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
 }
 
+/* Release Watchdog 1 from reset through reset manager */
+void socfpga_reset_deassert_wd1(void)
+{
+	clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
+		     ALT_RSTMGR_PER1MODRST_WD1_SET_MSK);
+}
+
 /*
  * Assert or de-assert SoCFPGA reset manager reset.
  */
@@ -154,15 +164,16 @@  void socfpga_per_reset(u32 reset, int set)
 }
 
 /*
- * Assert reset on every peripheral but L4WD0.
+ * Assert reset on every peripheral but L4WD0 & l4WD1.
  * Watchdog must be kept intact to prevent glitches
  * and/or hangs.
  * For the Arria10, we disable all the peripherals except L4 watchdog0,
- * L4 Timer 0, and ECC.
+ * L4 watchdog1, L4 Timer 0, and ECC.
  */
 void socfpga_per_reset_all(void)
 {
-	const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
+	const u32 l4wd = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
+			  1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD1)) |
 			  (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
 	unsigned mask_ecc_ocp =
 		ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
@@ -174,8 +185,8 @@  void socfpga_per_reset_all(void)
 		ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
 		ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
 
-	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
-	writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST);
+	/* disable all components except ECC_OCP, L4 Timer0, L4 WD0 & l4 WD1 */
+	writel(~l4wd, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST);
 	setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
 		     ~mask_ecc_ocp);
 
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index 96bad162df..5d661fb995 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -255,7 +255,7 @@  void board_init_f(ulong dummy)
 	socfpga_sdram_remap_zero();
 	socfpga_pl310_clear();
 
-	/* Assert reset to all except L4WD0 and L4TIMER0 */
+	/* Assert reset to all except L4WD0, L4WD1 and L4TIMER0 */
 	socfpga_per_reset_all();
 	socfpga_watchdog_disable();