diff mbox series

arm: socfpga: A10: Enable Designware watchdog

Message ID 20220919004621.31032-1-teik.heng.chong@intel.com
State Needs Review / ACK, archived
Delegated to: Marek Vasut
Headers show
Series arm: socfpga: A10: Enable Designware watchdog | expand

Commit Message

Chong, Teik Heng Sept. 19, 2022, 12:46 a.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

Some bootROMs enable the watchdog before jumping to SPL, so calling
WATCHDOG_RESET() is required to reset watchdog timely especially
in long looping. Enable Designware watchdog driver is required to
support WATCHDOG_RESET().

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
---
 arch/arm/mach-socfpga/Kconfig | 3 +++
 1 file changed, 3 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index df44530e83..505d30f9e4 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -64,8 +64,10 @@  config TARGET_SOCFPGA_ARRIA10
 	select SPL_ALTERA_SDRAM
 	select SPL_BOARD_INIT if SPL
 	select SPL_CACHE if SPL
+	select SPL_WDT if SPL
 	select CLK
 	select SPL_CLK if SPL
+	select DESIGNWARE_WATCHDOG
 	select DM_I2C
 	select DM_RESET
 	select SPL_DM_RESET if SPL
@@ -74,6 +76,7 @@  config TARGET_SOCFPGA_ARRIA10
 	select SYSCON
 	select SPL_SYSCON if SPL
 	select ETH_DESIGNWARE_SOCFPGA
+	select WDT
 	imply FPGA_SOCFPGA
 	imply SPL_USE_TINY_PRINTF