@@ -149,6 +149,7 @@ static unsigned int cadence_qspi_wait_idle(void *reg_base)
start = get_timer(0);
for ( ; get_timer(start) < timeout ; ) {
+ WATCHDOG_RESET();
if (CQSPI_REG_IS_IDLE(reg_base))
count++;
else
@@ -356,6 +357,7 @@ int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg)
if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
break;
udelay(1);
+ WATCHDOG_RESET();
}
if (!retry) {
@@ -652,6 +654,7 @@ static int cadence_qspi_wait_for_data(struct cadence_spi_plat *plat)
if (reg)
return reg;
udelay(1);
+ WATCHDOG_RESET();
}
return -ETIMEDOUT;
@@ -696,6 +699,7 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat,
rxbuf += bytes_to_read;
remaining -= bytes_to_read;
bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
+ WATCHDOG_RESET();
}
}
@@ -863,6 +867,7 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
bb_txbuf += write_bytes;
remaining -= write_bytes;
+ WATCHDOG_RESET();
}
/* Check indirect done status */