From patchwork Wed Aug 17 13:07:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Oberfichtner X-Patchwork-Id: 1667253 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=cq5/ewpC; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4M77bv0FTDz1yYg for ; Wed, 17 Aug 2022 23:07:55 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 90D1984A20; Wed, 17 Aug 2022 15:07:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1660741659; bh=e+sk51Njb/meYdgp2ljacnTEyVvnTNyMIkdMDMf1HQ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=cq5/ewpC67JL27dVwpAvxoVxbL3dNhC2M9Ev8b68CKTkO600K7y+aTY5com/qWvUO 2rRCc8Mhu0AX9G9Czx3kM5kA+21R4vu8IxqEE5zk4oHoSK0ZSi9UN9LyEx4FNRLem2 HmpogldSrRE8MFo0p10HN4nLschJZYFR8xjQdr5XA5ExZaRBVEzhq4uQPeopxS0fFH tuGslxo7+xqGm4HgzTrijnDjIMtmkRwyC4eXX741GBbaZYT8V9Px8VliYmYj1uxBwV fYQvvemga8A6dkBVhGMXFjJzSo8kajXqTBSYbq5fadfko9YFoXiOHBfZVCt7LBf0oe 2kzuFvTh6wXVw== Received: by phobos.denx.de (Postfix, from userid 109) id 288FF84A19; Wed, 17 Aug 2022 15:07:29 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.3 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,SPF_NEUTRAL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from xpert.denx.de (unknown [62.91.23.180]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B840284A1F for ; Wed, 17 Aug 2022 15:07:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=pro@denx.de Received: by xpert.denx.de (Postfix, from userid 535) id 7096F3E06F3; Wed, 17 Aug 2022 15:07:20 +0200 (CEST) From: Philip Oberfichtner To: u-boot@lists.denx.de Cc: Stefano Babic , Marek Vasut , Christoph Niedermaier , Philip Oberfichtner , Andreas Geisreiter , Tom Rini , u-boot@dh-electronics.com Subject: [PATCH v6 3/3] ARM: imx6: dh-imx6: Enable d-cache early in SPL Date: Wed, 17 Aug 2022 15:07:14 +0200 Message-Id: <20220817130714.3487965-4-pro@denx.de> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817130714.3487965-1-pro@denx.de> References: <20220817130714.3487965-1-pro@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Marek Vasut Enable d-cache early in SPL right after DRAM is started up. This reduces U-Boot proper load time by 650ms when loaded from SPI NOR. Signed-off-by: Marek Vasut Signed-off-by: Philip Oberfichtner --- Changes in v6: - Once more improve the dcache_disable() comment Changes in v5: - Clarify dcache_disable() comment Changes in v4: - Elaborate on dcache_disable() comment Changes in v3: - Use newly introduced Kconfig symbol for dh_imx6_defconfig Changes in v2: - Add comment to explain the relevance of dcache_disable() board/dhelectronics/dh_imx6/dh_imx6_spl.c | 41 +++++++++++++++++++++++ configs/dh_imx6_defconfig | 1 + 2 files changed, 42 insertions(+) diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index e49e97724a..20a330cce6 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -14,11 +15,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -610,6 +613,20 @@ static void dhcom_spl_dram_init(void) } } +void dram_bank_mmu_setup(int bank) +{ + int i; + + set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); + set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); + + for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT; + i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) + + (SZ_1G >> MMU_SECTION_SHIFT)); + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); +} + void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ @@ -636,9 +653,33 @@ void board_init_f(ulong dummy) /* DDR3 initialization */ dhcom_spl_dram_init(); + /* Set up early MMU tables at the beginning of DRAM and start d-cache */ + gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M; + gd->arch.tlb_size = PGTABLE_SIZE; + enable_caches(); + /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); } + +void spl_board_prepare_for_boot(void) +{ + /* + * Flush and disable dcache. Without it, the following bootstage might fail randomly because + * dirty cache lines may not have been written back to DRAM. + * + * If dcache_disable() would be omitted, the following scenario may occur: + * + * The SPL enables dcache and cachelines get populated with data. Then dcache gets disabled + * in U-Boot proper, but still contains dirty data, i.e. the corresponding DRAM locations + * have not yet been updated. When U-Boot reads these locations, it sees an (incorrect) old + * state of the content. + * + * Furthermore, the DRAM contents have likely been modified by U-Boot while dcache was + * disabled. Thus, U-Boot flushing dcache would corrupt DRAM with stale data. + */ + dcache_disable(); /* implies flush_dcache_all() */ +} diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 051816f719..1be6ae62ce 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SYS_L2_PL310=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_F_LEN=0x1000