From patchwork Wed Aug 17 09:06:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Oberfichtner X-Patchwork-Id: 1667179 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=WaEd1ydW; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4M72Fn33qsz1ygF for ; Wed, 17 Aug 2022 19:06:53 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B96F7849CB; Wed, 17 Aug 2022 11:06:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1660727203; bh=Dp5mniE7Fix49yXuLLiQI6HQMy4smIcol7JWF2OLg04=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=WaEd1ydWp9ZcidkDr1XAJePEQOWc7ujzQB+geb0N85v39lOgkZe0+0GIhXMvne2Zz Ol8bBb99amPv1F5kRL3iKsqRft0/kYUyEEw+cR/wibTsdtWh0lnOlVWTf1fYyZd4jG 6o4ZvxxqjZY2/PSnmnF/dCA/y888AM2PpzTRls2iEJ/X4kEPn1ewB+P6SEoOW3s6Xv EZiv5juK7bB9WT4BY54rbrFHLROmFiJ2/05MTjXcMeOXuL1u7UoOft/RfUZCjD1p02 V1q4i62oSfnlZy5kvUwz6rXWk1Y/p3IEprNnizTyvukDW+R0nETGzUC5h78TElYu6o i1v9W3OS/8NZA== Received: by phobos.denx.de (Postfix, from userid 109) id A7FFA849CB; Wed, 17 Aug 2022 11:06:39 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.3 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,SPF_NEUTRAL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from xpert.denx.de (unknown [62.91.23.180]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D44A8849F3 for ; Wed, 17 Aug 2022 11:06:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=pro@denx.de Received: by xpert.denx.de (Postfix, from userid 535) id 9082E3E06F3; Wed, 17 Aug 2022 11:06:36 +0200 (CEST) From: Philip Oberfichtner To: u-boot@lists.denx.de Cc: Stefano Babic , Marek Vasut , Christoph Niedermaier , Philip Oberfichtner , Andreas Geisreiter , Tom Rini , u-boot@dh-electronics.com Subject: [PATCH v4 3/3] ARM: imx6: dh-imx6: Enable d-cache early in SPL Date: Wed, 17 Aug 2022 11:06:11 +0200 Message-Id: <20220817090611.3292993-4-pro@denx.de> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817090611.3292993-1-pro@denx.de> References: <20220817090611.3292993-1-pro@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Marek Vasut Enable d-cache early in SPL right after DRAM is started up. This reduces U-Boot proper load time by 650ms when loaded from SPI NOR. Signed-off-by: Marek Vasut Signed-off-by: Philip Oberfichtner --- Changes in v4: - Elaborate on dcache_disable() comment Changes in v3: - Use newly introduced Kconfig symbol for dh_imx6_defconfig Changes in v2: - Add comment to explain the relevance of dcache_disable() board/dhelectronics/dh_imx6/dh_imx6_spl.c | 32 +++++++++++++++++++++++ configs/dh_imx6_defconfig | 1 + 2 files changed, 33 insertions(+) diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index e49e97724a..580b98811c 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -14,11 +15,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -610,6 +613,20 @@ static void dhcom_spl_dram_init(void) } } +void dram_bank_mmu_setup(int bank) +{ + int i; + + set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); + set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); + + for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT; + i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) + + (SZ_1G >> MMU_SECTION_SHIFT)); + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); +} + void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ @@ -636,9 +653,24 @@ void board_init_f(ulong dummy) /* DDR3 initialization */ dhcom_spl_dram_init(); + /* Set up early MMU tables at the beginning of DRAM and start d-cache */ + gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M; + gd->arch.tlb_size = PGTABLE_SIZE; + enable_caches(); + /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); } + +void spl_board_prepare_for_boot(void) +{ + /* + * Flush dcache. Without it U-Boot proper would hang at random locations. Presumably this is + * due to dirty cache lines remaining after SPL passes control. When U-Boot proper later on + * calls invalidate_dcache_all(), those dirty cache lines will get lost. + */ + dcache_disable(); +} diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 051816f719..1be6ae62ce 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SYS_L2_PL310=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_F_LEN=0x1000