Message ID | 20220804081533.2228257-2-pro@denx.de |
---|---|
State | Superseded |
Delegated to: | Tom Rini |
Headers | show |
Series | [1/2] ARM: cache: Allow SPL to build cache-pl310.c | expand |
On 8/4/22 10:15, Philip Oberfichtner wrote: > From: Marek Vasut <marex@denx.de> > > Enable d-cache early in SPL right after DRAM is started up. > This reduces U-Boot proper load time by 650ms when loaded > from SPI NOR. > > Signed-off-by: Marek Vasut <marex@denx.de> > Signed-off-by: Philip Oberfichtner <pro@denx.de> > > --- > > board/dhelectronics/dh_imx6/dh_imx6_spl.c | 27 +++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c > index e49e97724a..2c0ddc527a 100644 > --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c > +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c > @@ -6,6 +6,7 @@ > */ > > #include <common.h> > +#include <cpu_func.h> > #include <init.h> > #include <asm/arch/clock.h> > #include <asm/arch/crm_regs.h> > @@ -14,11 +15,13 @@ > #include <asm/arch/mx6-ddr.h> > #include <asm/arch/mx6-pins.h> > #include <asm/arch/sys_proto.h> > +#include <asm/cache.h> > #include <asm/gpio.h> > #include <asm/mach-imx/boot_mode.h> > #include <asm/mach-imx/iomux-v3.h> > #include <asm/mach-imx/mxc_i2c.h> > #include <asm/io.h> > +#include <asm/system.h> > #include <errno.h> > #include <fuse.h> > #include <fsl_esdhc_imx.h> > @@ -610,6 +613,20 @@ static void dhcom_spl_dram_init(void) > } > } > > +void dram_bank_mmu_setup(int bank) > +{ > + int i; > + > + set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); > + set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); > + > + for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT; > + i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) + > + (SZ_1G >> MMU_SECTION_SHIFT)); > + i++) > + set_section_dcache(i, DCACHE_DEFAULT_OPTION); > +} > + > void board_init_f(ulong dummy) > { > /* setup AIPS and disable watchdog */ > @@ -636,9 +653,19 @@ void board_init_f(ulong dummy) > /* DDR3 initialization */ > dhcom_spl_dram_init(); > > + /* Set up early MMU tables at the beginning of DRAM and start d-cache */ > + gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M; > + gd->arch.tlb_size = PGTABLE_SIZE; > + enable_caches(); > + > /* Clear the BSS. */ > memset(__bss_start, 0, __bss_end - __bss_start); > > /* load/boot image from boot device */ > board_init_r(NULL, 0); > } > + > +void spl_board_prepare_for_boot(void) > +{ An explanation why this is needed in a comment would be good to have. > + dcache_disable(); > +}
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index e49e97724a..2c0ddc527a 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <cpu_func.h> #include <init.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> @@ -14,11 +15,13 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> +#include <asm/cache.h> #include <asm/gpio.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/io.h> +#include <asm/system.h> #include <errno.h> #include <fuse.h> #include <fsl_esdhc_imx.h> @@ -610,6 +613,20 @@ static void dhcom_spl_dram_init(void) } } +void dram_bank_mmu_setup(int bank) +{ + int i; + + set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); + set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); + + for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT; + i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) + + (SZ_1G >> MMU_SECTION_SHIFT)); + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); +} + void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ @@ -636,9 +653,19 @@ void board_init_f(ulong dummy) /* DDR3 initialization */ dhcom_spl_dram_init(); + /* Set up early MMU tables at the beginning of DRAM and start d-cache */ + gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M; + gd->arch.tlb_size = PGTABLE_SIZE; + enable_caches(); + /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); } + +void spl_board_prepare_for_boot(void) +{ + dcache_disable(); +}