@@ -22,6 +22,7 @@ xilinx_desc fpga = {
.family = xilinx_zynq,
.iface = devcfg,
.operations = &zynq_op,
+ .flags = FPGA_LEGACY,
};
#endif
@@ -27,7 +27,10 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_FPGA_VERSALPL)
-static xilinx_desc versalpl = XILINX_VERSAL_DESC;
+static xilinx_desc versalpl = {
+ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
+ FPGA_LEGACY
+};
#endif
int board_init(void)
@@ -48,7 +48,10 @@
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
-static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
+static xilinx_desc zynqmppl = {
+ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op, NULL,
+ ZYNQMP_FPGA_FLAGS
+};
#endif
int __maybe_unused psu_uboot_init(void)
@@ -14,7 +14,4 @@
extern struct xilinx_fpga_op versal_op;
-#define XILINX_VERSAL_DESC \
-{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op }
-
#endif /* _VERSALPL_H_ */
@@ -37,6 +37,9 @@ typedef enum { /* typedef xilinx_family */
max_xilinx_type /* insert all new types before this */
} xilinx_family; /* end, typedef xilinx_family */
+/* FPGA bitstream supported types */
+#define FPGA_LEGACY BIT(0)
+
typedef struct { /* typedef xilinx_desc */
xilinx_family family; /* part type */
xilinx_iface iface; /* interface type */
@@ -45,6 +48,7 @@ typedef struct { /* typedef xilinx_desc */
int cookie; /* implementation specific cookie */
struct xilinx_fpga_op *operations; /* operations */
char *name; /* device name in bitstream */
+ int flags; /* compatible flags */
} xilinx_desc; /* end, typedef xilinx_desc */
struct xilinx_fpga_op {
@@ -25,7 +25,6 @@
extern struct xilinx_fpga_op zynqmp_op;
-#define XILINX_ZYNQMP_DESC \
-{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
+#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY)
#endif /* _ZYNQMPPL_H_ */