diff mbox series

[03/10] board: sl28: set CPO value

Message ID 20220530210214.2816812-4-michael@walle.cc
State Accepted
Commit 6bdda4b2003fadbcbcc28a1d395ec1f6f6557539
Delegated to: Peng Fan
Headers show
Series board: sl28: various updates | expand

Commit Message

Michael Walle May 30, 2022, 9:02 p.m. UTC 
With a 8GiB memory board, it seems that the "very unlikely event" of a
DDR initialization with non-optimal values are not really that unlikely.
It happens in about every other reboot. As described in erratum
A-009942, preset the DEBUG_28 register with an optimal value. The value
iself depends on the memory configuration of the board, but the used
value seems to work well for all variants.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 board/kontron/sl28/ddr.c | 3 +++
 1 file changed, 3 insertions(+)
diff mbox series

Patch

diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c
index 41426996ab..d75b23e54c 100644
--- a/board/kontron/sl28/ddr.c
+++ b/board/kontron/sl28/ddr.c
@@ -54,6 +54,9 @@  static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = {
 
 	.ddr_cdr1		= 0x80040000,
 	.ddr_cdr2		= 0x0000bc01,
+
+	/* Erratum A-009942, set optimal CPO value */
+	.debug[28]		= 0x00700040,
 };
 
 int fsl_initdram(void)