From patchwork Thu May 19 11:08:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Oberfichtner X-Patchwork-Id: 1633154 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=bEe+SSvX; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L3nDn4kTQz9tkb for ; Thu, 19 May 2022 21:09:29 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F422683D0C; Thu, 19 May 2022 13:09:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1652958554; bh=Kkz6GJfEY5Ie17QdXVDOy6kwCkU76mSqBwCje8PGnEE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=bEe+SSvXU8BOSilE4IkVI+VmwsvX7y5YUHWp28pbL83kJWTNCQpcdldnMx3kAMstH 44dTZQIh78MjEGlqSqTjHHWLOZ7/TNEz5XEmOYKooWLeEvxWNM55IKR1bYqHQ9iti/ vqpMIGqLn5nHfh8eP6TMh6mTlMf2Gz7sSwILC5na4c1ApGLz4IekxtZ2L3w35MAVxT r7ZIzbfeA1H3hb8sa+tRN+FzAKJljpK7Id3oU9k4OHw5J6fb1j65IY7FAx0xzyTDUZ uFaA+P8ETWf4wbHnzVNzkyV1kpU+E32nFbOo0CA/dEVzDGGsEwKcKZPWVwAzaJ7VWo 3z5orJ+5M7vpA== Received: by phobos.denx.de (Postfix, from userid 109) id 3400083F48; Thu, 19 May 2022 13:09:04 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.3 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,SPF_NEUTRAL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from xpert.denx.de (unknown [62.91.23.180]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C0AD383D0C for ; Thu, 19 May 2022 13:08:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=pro@denx.de Received: by xpert.denx.de (Postfix, from userid 535) id 847103E0EA9; Thu, 19 May 2022 13:08:58 +0200 (CEST) From: Philip Oberfichtner To: u-boot@lists.denx.de Cc: Fabio Estevam , Christoph Niedermaier , Stefano Babic , Peng Fan , Philip Oberfichtner , Marek Vasut , Andre Przywara , Andreas Geisreiter , Christian Hewitt , Fabio Estevam , Jagan Teki , "NXP i.MX U-Boot Team" , Neil Armstrong , Simon Glass , Sinthu Raja , Tim Harvey , Tom Rini , "Ying-Chun Liu (PaulLiu)" , u-boot@dh-electronics.com Subject: [PATCH 2/8] ARM: dts: imx: Migrate iMX6QDL DRC02 DTs from Linux Date: Thu, 19 May 2022 13:08:31 +0200 Message-Id: <20220519110837.245488-3-pro@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220519110837.245488-1-pro@denx.de> References: <20220519110837.245488-1-pro@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Migrate DH DRC02 device trees from Linux commit 42226c989789 (tag v5.18-rc7). No changes have been made, the DTs are exact copies. Furthermore add the DTB to dh_imx6_defconfig. Reviewed-by: Marek Vasut Signed-off-by: Philip Oberfichtner --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6qdl-dhcom-drc02.dtsi | 143 ++++++++++++++++++++++++++ arch/arm/dts/imx6s-dhcom-drc02.dts | 30 ++++++ configs/dh_imx6_defconfig | 2 +- 4 files changed, 175 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6qdl-dhcom-drc02.dtsi create mode 100644 arch/arm/dts/imx6s-dhcom-drc02.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 83630af4f6..7bfdfb5313 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -771,6 +771,7 @@ dtb-y += \ imx6dl-sabreauto.dtb \ imx6dl-sabresd.dtb \ imx6dl-wandboard-revd1.dtb \ + imx6s-dhcom-drc02.dtb endif diff --git a/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi b/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi new file mode 100644 index 0000000000..702cd4a1b2 --- /dev/null +++ b/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* + * Special SoM hardware required which uses the pins from micro SD card. The + * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 + * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD + * card must be disabled and the uart1 rts/cts must be output on other DHCOM + * pins, see uart1 and usdhc3 node below. + */ +&can2 { + status = "okay"; +}; + +&gpio1 { + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the i.MX6 UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en-hog { + gpio-hog; + gpios = <18 0>; /* GPIO Q */ + line-name = "rs485-rx-en"; + output-low; + }; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "DRC02-In1", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H", + "DHCOM-I", "DRC02-HW0", "", "", "", "", "", "", + "", "", "", "", "DRC02-Out1", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "DRC02-Out2", "", "", "SOM-HW1", "", + "", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&uart1 { + /* + * Due to the use of can2 the signals for can2 Tx and Rx are routed to + * DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs + * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts. + */ + /delete-property/ uart-has-rtscts; + cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */ + pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>; + pinctrl-names = "default"; + rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ +}; + +&uart5 { + /* + * On DRC02 this UART is used as RS485 interface and RS485_TX_En is + * controlled by DHCOM GPIO P. So remove rts/cts pins and the property + * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via + * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1 + * node above. + */ + /delete-property/ uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + pinctrl-0 = <&pinctrl_uart5_core &pinctrl_dhcom_p &pinctrl_dhcom_q>; + pinctrl-names = "default"; + rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */ +}; + +&usbh1 { + disable-over-current; +}; + +&usdhc2 { /* SD card */ + status = "okay"; +}; + +&usdhc3 { + /* + * Due to the use of can2 the micro SD card on module have to be + * disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as + * can2 Tx and Rx. + */ + status = "disabled"; +}; + +&iomuxc { + pinctrl-0 = < + /* + * The following DHCOM GPIOs are used on this board. + * Therefore, they have been removed from the list below. + * I: uart1 rts + * M: uart1 cts + * P: uart5 rs485-tx-en + * Q: uart5 rs485-rx-en + */ + &pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u + &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int + >; + pinctrl-names = "default"; + + pinctrl_uart5_core: uart5-core-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/dts/imx6s-dhcom-drc02.dts b/arch/arm/dts/imx6s-dhcom-drc02.dts new file mode 100644 index 0000000000..4077b607c2 --- /dev/null +++ b/arch/arm/dts/imx6s-dhcom-drc02.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + * + * DHCOM iMX6 variant: + * DHCM-iMX6S-C0800-R102-F0409-E-CAN2-RTC-I-01D2 + * DHCOM PCB number: 493-400 or newer + * DRC02 PCB number: 568-100 or newer + */ +/dts-v1/; + +/* + * The kernel only distinguishes between i.MX6 Quad and DualLite, + * but the Solo is actually a DualLite with only one CPU. So use + * DualLite for the Solo and disable one CPU node. + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-dhcom-som.dtsi" +#include "imx6qdl-dhcom-drc02.dtsi" + +/ { + model = "DH electronics i.MX6S DHCOM on DRC02"; + compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som", + "fsl,imx6dl"; + + cpus { + /delete-node/ cpu@1; + }; +}; diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index c45561aa0e..9c78987473 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -53,7 +53,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2" +CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2 imx6s-dhcom-drc02" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y