@@ -87,37 +87,20 @@ static void spl_dram_init(int size)
ddr_init(dram_timing);
}
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#ifdef CONFIG_IMX8MM
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#elif CONFIG_IMX8MN
-static const iomux_v3_cfg_t uart_pads[] = {
- IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static const iomux_v3_cfg_t wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#elif CONFIG_IMX8MP
-static const iomux_v3_cfg_t uart_pads[] = {
- MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static const iomux_v3_cfg_t wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
-
#endif
int board_early_init_f(void)
@@ -128,8 +111,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
return 0;
}
@@ -276,8 +257,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -287,6 +266,8 @@ void board_init_f(ulong dummy)
hang();
}
+ preloader_console_init();
+
enable_tzc380();
/* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
@@ -114,7 +114,6 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
@@ -113,7 +113,6 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
@@ -113,7 +113,6 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
The uart2 and its pinmux are already marked with u-boot,dm-spl but we need to move the call to preloader_console_init() after spl_early_init() to avoid a board hang as dm can't be used until after spl_early_init() due to the uart driver not enabling the uart clock. Remove the manual config of the UART pinmux now that it is no longer needed. Signed-off-by: Tim Harvey <tharvey@gateworks.com> --- board/gateworks/venice/spl.c | 23 ++--------------------- configs/imx8mm_venice_defconfig | 1 - configs/imx8mn_venice_defconfig | 1 - configs/imx8mp_venice_defconfig | 1 - 4 files changed, 2 insertions(+), 24 deletions(-)