From patchwork Thu Apr 21 06:23:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1619950 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KkSF10282z9sFN for ; Thu, 21 Apr 2022 16:24:36 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0611B831CA; Thu, 21 Apr 2022 08:24:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id A40DC83B9E; Thu, 21 Apr 2022 08:24:32 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, RDNS_NONE,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7D014830AF for ; Thu, 21 Apr 2022 08:24:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sam.shih@mediatek.com X-UUID: 16e1381b7c554ffab185df1e6f5aab0c-20220421 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:06c2fb13-4574-48fe-9587-40e85dd28738, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9, CLOUDID:cc5d72f0-da02-41b4-b6df-58f4ccd36682, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 16e1381b7c554ffab185df1e6f5aab0c-20220421 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1551891047; Thu, 21 Apr 2022 14:24:24 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 21 Apr 2022 14:24:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 21 Apr 2022 14:24:22 +0800 From: Sam Shih To: Tom Rini , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream , CC: Sam Shih Subject: [PATCH v4 1/3] pinctrl: mediatek: rewrite mtk_pinconf_set and related functions Date: Thu, 21 Apr 2022 14:23:51 +0800 Message-ID: <20220421062353.12085-2-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220421062353.12085-1-sam.shih@mediatek.com> References: <20220421062353.12085-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean There are many pins in a SoCs, and different pin may belong to different "io_type", For example: some pins of MT7622 belongs to "io_type A", the other belongs to "io_type B", and pinctrl "V0" means handle pinconf via "io_type A" or "io_type B", so SoCs that contain "io_type A" and "io_type B" pins, use "V0" in pinctrl driver. This patch separates the implementation of register operations (e.g: "bias-pull-up/down", "driving" and "input-enable") into different functions, and lets the original V0/V1 ops to call the new functions. Signed-off-by: Sam Shih --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 126 +++++++++++++----- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 18 +++ 2 files changed, 114 insertions(+), 30 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index a9cedda164..4ae328699e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -308,13 +308,31 @@ static const struct pinconf_param mtk_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, }; +int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val) +{ + return mtk_pinconf_bias_set_pu_pd(dev, pin, disable, pullup, val); +} -int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg, u32 val) +int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val) { - int err, disable, pullup; + int err; - disable = (arg == PIN_CONFIG_BIAS_DISABLE); - pullup = (arg == PIN_CONFIG_BIAS_PULL_UP); + /* try pupd_r1_r0 if pullen_pullsel return error */ + err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup, + val); + if (err) + return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable, + pullup, val); + + return err; +} + +int mtk_pinconf_bias_set_pu_pd(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val) +{ + int err; if (disable) { err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, 0); @@ -323,7 +341,6 @@ int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg, u32 val) err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, 0); if (err) return err; - } else { err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, pullup); if (err) @@ -336,14 +353,10 @@ int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg, u32 val) return 0; } -int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg, u32 val) +int mtk_pinconf_bias_set_pullen_pullsel(struct udevice *dev, u32 pin, + bool disable, bool pullup, u32 val) { - int err, disable, pullup, r0, r1; - - disable = (arg == PIN_CONFIG_BIAS_DISABLE); - pullup = (arg == PIN_CONFIG_BIAS_PULL_UP); - r0 = !!(val & 1); - r1 = !!(val & 2); + int err; if (disable) { err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 0); @@ -359,16 +372,53 @@ int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg, u32 val) return err; } - /* Also set PUPD/R0/R1 if the pin has them */ - err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup); - if (err != -EINVAL) { - mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0); - mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1); + return 0; +} + +int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val) +{ + int err, r0, r1; + + r0 = !!(val & 1); + r1 = !!(val & 2); + + if (disable) { + pullup = 0; + r0 = 0; + r1 = 0; } + /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */ + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup); + if (err) + return err; + + /* Also set PUPD/R0/R1 if the pin has them */ + mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0); + mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1); + return 0; } +int mtk_pinconf_bias_set(struct udevice *dev, u32 pin, u32 arg, u32 val) +{ + int err; + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + int rev = priv->soc->rev; + bool disable, pullup; + + disable = (arg == PIN_CONFIG_BIAS_DISABLE); + pullup = (arg == PIN_CONFIG_BIAS_PULL_UP); + + if (rev == MTK_PINCTRL_V0) + err = mtk_pinconf_bias_set_v0(dev, pin, disable, pullup, val); + else + err = mtk_pinconf_bias_set_v1(dev, pin, disable, pullup, val); + + return err; +} + int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg) { int err; @@ -379,6 +429,18 @@ int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg) err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0); if (err) return err; + + return 0; +} + +int mtk_pinconf_input_enable(struct udevice *dev, u32 pin, u32 arg) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + int rev = priv->soc->rev; + + if (rev == MTK_PINCTRL_V1) + return mtk_pinconf_input_enable_v1(dev, pin, arg); + return 0; } @@ -410,7 +472,6 @@ int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg) return 0; } - int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg) { struct mtk_pinctrl_priv *priv = dev_get_priv(dev); @@ -429,21 +490,30 @@ int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg) return 0; } +int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg) +{ + int err; + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + int rev = priv->soc->rev; + + if (rev == MTK_PINCTRL_V0) + err = mtk_pinconf_drive_set_v0(dev, pin, arg); + else + err = mtk_pinconf_drive_set_v1(dev, pin, arg); + + return err; +} + static int mtk_pinconf_set(struct udevice *dev, unsigned int pin, unsigned int param, unsigned int arg) { int err = 0; - struct mtk_pinctrl_priv *priv = dev_get_priv(dev); - int rev = priv->soc->rev; switch (param) { case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: - if (rev == MTK_PINCTRL_V0) - err = mtk_pinconf_bias_set_v0(dev, pin, param, arg); - else - err = mtk_pinconf_bias_set_v1(dev, pin, param, arg); + err = mtk_pinconf_bias_set(dev, pin, param, arg); if (err) goto err; break; @@ -456,8 +526,7 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin, goto err; break; case PIN_CONFIG_INPUT_ENABLE: - if (rev == MTK_PINCTRL_V1) - err = mtk_pinconf_input_enable_v1(dev, pin, param); + err = mtk_pinconf_input_enable(dev, pin, param); if (err) goto err; break; @@ -486,10 +555,7 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin, goto err; break; case PIN_CONFIG_DRIVE_STRENGTH: - if (rev == MTK_PINCTRL_V0) - err = mtk_pinconf_drive_set_v0(dev, pin, arg); - else - err = mtk_pinconf_drive_set_v1(dev, pin, arg); + err = mtk_pinconf_drive_set(dev, pin, arg); if (err) goto err; break; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 5e51a9a90c..735fb6fef8 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -192,4 +192,22 @@ void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set); int mtk_pinctrl_common_probe(struct udevice *dev, struct mtk_pinctrl_soc *soc); +#if CONFIG_IS_ENABLED(PINCONF) + +int mtk_pinconf_bias_set_pu_pd(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val); +int mtk_pinconf_bias_set_pullen_pullsel(struct udevice *dev, u32 pin, + bool disable, bool pullup, u32 val); +int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val); +int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val); +int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val); +int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg); +int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg); +int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg); + +#endif + #endif /* __PINCTRL_MEDIATEK_H__ */