From patchwork Fri Apr 15 14:09:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1617845 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=uveBZ+oV; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KfytZ2bdmz9sFq for ; Sat, 16 Apr 2022 00:11:34 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A3FB883DE0; Fri, 15 Apr 2022 16:10:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="uveBZ+oV"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id F1E2C839B3; Fri, 15 Apr 2022 16:10:28 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9059083DA6 for ; Fri, 15 Apr 2022 16:10:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=vigneshr@ti.com Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 23FEALle100469; Fri, 15 Apr 2022 09:10:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1650031821; bh=UiMqUeA39/ifZGTjRqXCGVyM3VA4TSm9Qf26GxGv4VA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uveBZ+oV2zaLpzMIHGkdpC9nCqOL7bvaEvRraiM54p7UTHbLdHAvCSpIrHAcy+mu/ RDgovbyTiSqF3g+X3P/W/hZBHVLzFCp06u7s1ZorG9Kvcpu2rck0Ep0GpjZ48/lxOc Gcr7l7tUOSgybtvXJyHJPTvznVzzBxyLPELz+RTU= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 23FEALSN056637 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 15 Apr 2022 09:10:21 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 15 Apr 2022 09:10:21 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 15 Apr 2022 09:10:20 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23FE9WRr090004; Fri, 15 Apr 2022 09:10:16 -0500 From: Vignesh Raghavendra To: Tom Rini , Dave Gerlach , Lukasz Majewski , Sean Anderson , Peng Fan , Jaehoon Chung CC: Simon Glass , Vignesh Raghavendra , Suman Anna , Nishanth Menon , Aswath Govindraju , Bryan Brattlof , , Georgi Vlaev Subject: [PATCH 08/11] board: ti: Introduce the basic files to support AM62 SK board Date: Fri, 15 Apr 2022 19:39:28 +0530 Message-ID: <20220415140931.490047-9-vigneshr@ti.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220415140931.490047-1-vigneshr@ti.com> References: <20220415140931.490047-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Suman Anna Add basic support for AM64 SK. This has 2GB DDR. Note that stack for R5 SPL is in OCRAM @ 0x7000ffff so that is away from BSS and does not step on BSS section Signed-off-by: Suman Anna Signed-off-by: Aswath Govindraju Signed-off-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/Kconfig | 1 + board/ti/am62x/Kconfig | 63 +++++++++++ board/ti/am62x/Makefile | 8 ++ board/ti/am62x/evm.c | 149 ++++++++++++++++++++++++++ drivers/firmware/ti_sci_static_data.h | 7 ++ 5 files changed, 228 insertions(+) create mode 100644 board/ti/am62x/Kconfig create mode 100644 board/ti/am62x/Makefile create mode 100644 board/ti/am62x/evm.c diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 0dc4f44fdd..57f693e9a1 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -178,6 +178,7 @@ config K3_DM_FW source "board/ti/am65x/Kconfig" source "board/ti/am64x/Kconfig" +source "board/ti/am62x/Kconfig" source "board/ti/j721e/Kconfig" source "board/siemens/iot2050/Kconfig" source "board/ti/j721s2/Kconfig" diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig new file mode 100644 index 0000000000..95eec27170 --- /dev/null +++ b/board/ti/am62x/Kconfig @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ +# Suman Anna + +choice + prompt "TI K3 AM62x based boards" + optional + +config TARGET_AM625_A53_EVM + bool "TI K3 based AM625 EVM running on A53" + select ARM64 + select SOC_K3_AM625 + imply BOARD + imply SPL_BOARD + imply TI_I2C_BOARD_DETECT + +config TARGET_AM625_R5_EVM + bool "TI K3 based AM625 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select SOC_K3_AM625 + select RAM + select SPL_RAM + select K3_DDRSS + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + +endchoice + +if TARGET_AM625_A53_EVM + +config SYS_BOARD + default "am62x" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am62x_evm" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_AM625_R5_EVM + +config SYS_BOARD + default "am62x" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am62x_evm" + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +source "board/ti/common/Kconfig" + +endif diff --git a/board/ti/am62x/Makefile b/board/ti/am62x/Makefile new file mode 100644 index 0000000000..f4c35edffa --- /dev/null +++ b/board/ti/am62x/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ +# Suman Anna +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evm.o diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c new file mode 100644 index 0000000000..cf25f0acd9 --- /dev/null +++ b/board/ti/am62x/evm.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board specific initialization for AM62x platforms + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Suman Anna + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../common/board_detect.h" + +#define board_is_am62x_skevm() board_ti_k3_is("AM62-SKEVM") + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x80000000; + + return 0; +} + +int dram_init_banksize(void) +{ + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + + return 0; +} + +#if defined(CONFIG_SPL_LOAD_FIT) +int board_fit_config_name_match(const char *name) +{ + bool eeprom_read = board_ti_was_eeprom_read(); + + if (!eeprom_read || board_is_am62x_skevm()) { + if (!strcmp(name, "k3-am625-r5-sk") || !strcmp(name, "k3-am625-sk")) + return 0; + } + + return -1; +} +#endif + +#ifdef CONFIG_TI_I2C_BOARD_DETECT +int do_board_detect(void) +{ + int ret; + + ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS); + if (ret) { + printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n", + CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1); + ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS + 1); + if (ret) + pr_err("Reading on-board EEPROM at 0x%02x failed %d\n", + CONFIG_EEPROM_CHIP_ADDRESS + 1, ret); + } + + return ret; +} + +int checkboard(void) +{ + struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA; + + if (!do_board_detect()) + printf("Board: %s rev %s\n", ep->name, ep->version); + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +static void setup_board_eeprom_env(void) +{ + char *name = "am62x_skevm"; + + if (do_board_detect()) + goto invalid_eeprom; + + if (board_is_am62x_skevm()) + name = "am62x_skevm"; + else + printf("Unidentified board claims %s in eeprom header\n", + board_ti_get_name()); + +invalid_eeprom: + set_board_info_env_am6(name); +} + +static void setup_serial(void) +{ + struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA; + unsigned long board_serial; + char *endp; + char serial_string[17] = { 0 }; + + if (env_get("serial#")) + return; + + board_serial = simple_strtoul(ep->serial, &endp, 16); + if (*endp != '\0') { + pr_err("Error: Can't set serial# to %s\n", ep->serial); + return; + } + + snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial); + env_set("serial#", serial_string); +} +#endif +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) { + struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA; + + setup_board_eeprom_env(); + setup_serial(); + /* + * The first MAC address for ethernet a.k.a. ethernet0 comes from + * efuse populated via the am654 gigabit eth switch subsystem driver. + * All the other ones are populated via EEPROM, hence continue with + * an index of 1. + */ + board_ti_am6_set_ethaddr(1, ep->mac_addr_cnt); + } + + return 0; +} +#endif diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h index e6a3b66c03..21e783cc45 100644 --- a/drivers/firmware/ti_sci_static_data.h +++ b/drivers/firmware/ti_sci_static_data.h @@ -118,6 +118,13 @@ static struct ti_sci_resource_static_data rm_static_data[] = { }; #endif /* CONFIG_TARGET_J721S2_R5_EVM */ +#if IS_ENABLED(CONFIG_TARGET_AM625_R5_EVM) +static struct ti_sci_resource_static_data rm_static_data[] = { + { }, +}; + +#endif /* CONFIG_TARGET_AM625_R5_EVM */ + #else static struct ti_sci_resource_static_data rm_static_data[] = { { },