From patchwork Fri Apr 1 08:24:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1612087 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KVCsk2fWxz9sFy for ; Fri, 1 Apr 2022 19:25:30 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 87AC784289; Fri, 1 Apr 2022 10:24:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 4436C84288; Fri, 1 Apr 2022 10:24:42 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8493484276 for ; Fri, 1 Apr 2022 10:24:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sam.shih@mediatek.com X-UUID: 05d8a1f416f44752b65cd6b177343d7f-20220401 X-UUID: 05d8a1f416f44752b65cd6b177343d7f-20220401 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 67735190; Fri, 01 Apr 2022 16:24:20 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 1 Apr 2022 16:24:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 1 Apr 2022 16:24:19 +0800 From: Sam Shih To: Tom Rini , Ryder Lee , "Weijie Gao" , Chunfeng Yun , GSS_MTK_Uboot_upstream , CC: Sam Shih Subject: [v2, 3/3] pinctrl: mediatek: add support for different types of IO pins Date: Fri, 1 Apr 2022 16:24:07 +0800 Message-ID: <20220401082407.9759-4-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220401082407.9759-1-sam.shih@mediatek.com> References: <20220401082407.9759-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean There are many pins in an SoC, and register usage may vary by pins. This patch introduces a concept of "io type" and "io type group" to mediatek pinctrl drivers. This can provide different pinconf handlers implementation (eg: "bias-pull-up/down", "driving" and "input-enable") for IO pins that belong to different types. Signed-off-by: Sam Shih --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 48 +++++++++++++++++-- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 38 ++++++++++++++- 2 files changed, 80 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index bca60c4042..6f9b85871e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -69,7 +69,7 @@ static inline int get_count_order(unsigned int count) return order; } -void mtk_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set) +void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set) { return mtk_i_rmw(dev, 0, reg, mask, set); } @@ -219,6 +219,23 @@ static int mtk_hw_get_value(struct udevice *dev, int pin, int field, return 0; } +static int mtk_get_pin_io_type(struct udevice *dev, int pin, + struct mtk_io_type_desc *io_type) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + u8 io_n = priv->soc->pins[pin].io_n; + + if (io_n >= priv->soc->ntype) + return -EINVAL; + + io_type->name = priv->soc->io_type[io_n].name; + io_type->bias_set = priv->soc->io_type[io_n].bias_set; + io_type->drive_set = priv->soc->io_type[io_n].drive_set; + io_type->input_enable = priv->soc->io_type[io_n].input_enable; + + return 0; +} + static int mtk_get_groups_count(struct udevice *dev) { struct mtk_pinctrl_priv *priv = dev_get_priv(dev); @@ -416,16 +433,25 @@ int mtk_pinconf_bias_set(struct udevice *dev, u32 pin, u32 arg, u32 val) { int err; struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + struct mtk_io_type_desc io_type; int rev = priv->soc->rev; bool disable, pullup; disable = (arg == PIN_CONFIG_BIAS_DISABLE); pullup = (arg == PIN_CONFIG_BIAS_PULL_UP); - if (rev == MTK_PINCTRL_V0) + if (!mtk_get_pin_io_type(dev, pin, &io_type)) { + if (io_type.bias_set) + err = io_type.bias_set(dev, pin, disable, pullup, + val); + else + err = -EINVAL; + + } else if (rev == MTK_PINCTRL_V0) { err = mtk_pinconf_bias_set_v0(dev, pin, disable, pullup, val); - else + } else { err = mtk_pinconf_bias_set_v1(dev, pin, disable, pullup, val); + } return err; } @@ -447,8 +473,13 @@ int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg) int mtk_pinconf_input_enable(struct udevice *dev, u32 pin, u32 arg) { struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + struct mtk_io_type_desc io_type; + int rev = priv->soc->rev; + if (!mtk_get_pin_io_type(dev, pin, &io_type)) + if (io_type.input_enable) + return io_type.input_enable(dev, pin, arg); if (rev == MTK_PINCTRL_V1) return mtk_pinconf_input_enable_v1(dev, pin, arg); @@ -505,12 +536,19 @@ int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg) { int err; struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + struct mtk_io_type_desc io_type; int rev = priv->soc->rev; - if (rev == MTK_PINCTRL_V0) + if (!mtk_get_pin_io_type(dev, pin, &io_type)) { + if (io_type.drive_set) + err = io_type.drive_set(dev, pin, arg); + else + err = -EINVAL; + } else if (rev == MTK_PINCTRL_V0) { err = mtk_pinconf_drive_set_v0(dev, pin, arg); - else + } else { err = mtk_pinconf_drive_set_v1(dev, pin, arg); + } return err; } diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 91a8c0581f..0d9596fa72 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -12,10 +12,15 @@ #define MAX_BASE_CALC 10 #define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } -#define MTK_PIN(_number, _name, _drv_n) { \ + +#define MTK_PIN(_number, _name, _drv_n) \ + MTK_TYPED_PIN(_number, _name, _drv_n, IO_TYPE_DEFAULT) + +#define MTK_TYPED_PIN(_number, _name, _drv_n, _io_n) { \ .number = _number, \ .name = _name, \ .drv_n = _drv_n, \ + .io_n = _io_n, \ } #define PINCTRL_PIN_GROUP(name, id) \ @@ -75,6 +80,18 @@ enum { DRV_GRP4, }; +/* Group the pins by the io type */ +enum { + IO_TYPE_DEFAULT, + IO_TYPE_GRP0, + IO_TYPE_GRP1, + IO_TYPE_GRP2, + IO_TYPE_GRP3, + IO_TYPE_GRP4, + IO_TYPE_GRP5, + IO_TYPE_GRP6, +}; + /** * struct mtk_pin_field - the structure that holds the information of the field * used to describe the attribute for the pin @@ -139,11 +156,13 @@ struct mtk_pin_reg_calc { * @number: unique pin number from the global pin number space * @name: name for this pin * @drv_n: the index with the driving group + * @io_n: the index with the io type */ struct mtk_pin_desc { unsigned int number; const char *name; u8 drv_n; + u8 io_n; }; /** @@ -172,6 +191,21 @@ struct mtk_function_desc { int num_group_names; }; +/** + * struct mtk_io_type_desc - io class descriptor for specific pins + * @name: name of the io class + */ +struct mtk_io_type_desc { + const char *name; +#if CONFIG_IS_ENABLED(PINCONF) + /* Specific pinconfig operations */ + int (*bias_set)(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val); + int (*drive_set)(struct udevice *dev, u32 pin, u32 arg); + int (*input_enable)(struct udevice *dev, u32 pin, u32 arg); +#endif +}; + /* struct mtk_pin_soc - the structure that holds SoC-specific data */ struct mtk_pinctrl_soc { const char *name; @@ -182,6 +216,8 @@ struct mtk_pinctrl_soc { int ngrps; const struct mtk_function_desc *funcs; int nfuncs; + const struct mtk_io_type_desc *io_type; + u8 ntype; int gpio_mode; const char * const *base_names; unsigned int nbase_names;